Future wireless communication systems will have higher data transmission rates and energy efficiencies than those used today. This fact raises serious challenges to the design of conventional transceiver architectures. This doctoral research develops energy-efficient RF transmitters and receivers for next-generation wireless communications. It begins with a theoretical analysis of the injection locking of oscillators and a modified Class-E power amplifier (PA) for use in developing the proposed transmitter and receiver. Based on the presented theory, a novel envelope elimination and restoration (EER)/polar transmitter using injection-locked oscillators (ILOs) and a novel cognitive polar receiver using two ILO stages are proposed. The EER/polar transmitter combines the approaches of EER/polar modulation and injection locking to achieve linear amplification with a high gain and high efficiency. Experimental results demonstrate its effectiveness for delivering WCDMA and EDGE signals. Additionally, the cognitive polar receiver utilizes two ILO stages to extract the modulation envelope and phase components of a received nonconstant envelope modulation signal without using a phase-locked loop (PLL)-based carrier recovery circuit. Experiments are conducted to verify the feasibility of the novel architecture by performing £k/4 DQPSK and QPSK demodulation. Rigorous theoretical analysis and experimental verification prove that both the proposed transmitter and the receiver are effective for energy-efficient wireless communications.

This thesis improved the structure of traditional envelope elimination and restoration transmitter by replacing the analog components of envelope detector and limiter using digital processing technique of polar transformation. Envelope signal was modulated by delta-sigma modulation, which could suppress the quantization noise and would be good for integrated circuit design. The front end analog circuits of transmitter used high efficiency class-S and class-E power amplifiers to amplify envelope and phase signal separately and finally combined them at the output of class-E power amplifier. The RF transmitters using polar modulation had advantages of high efficiency and linearity when transmitting high PAPR-valued digital modulation signals. For example, when transmitting the QPSK-modulated signal with 900MHz carrier and 1Msps data rate, the transmitter was measured with efficiency as high as 60%, ACPR above 34dB, and EVM less than 6.5%.

Abstract¡G This thesis mainly implemented an RF transmitter with high efficiency and high linearity. A Cartesian to Polar transformation was implemented by CORDIC algorithm using FPGA. By replacing the envelope detector and limiter in traditional envelope elimination and restoration transmitter, this technique not only achieves more accurate modulation quality, but also becomes more suitable for single chip system. Applying the first order delta-sigma modulation and highly efficient switching-mode DC converter, the envelope signal was amplified highly efficiently. Due to the class-E power amplifier having good linear relation between output voltage and supply voltage, the polar modulation transmitter can achieve high efficiency and high linearity simultaneously. Furthermore, this thesis purposed a new transmitter with two-terminal time-varying modulation. The IQ modulated signal was fed to the input terminal of class-E amplifier, while the envelope signal was used to amplitude modulate the voltage supply terminal. With dynamic input power control, the conversion efficiency and linearity are independent of output power in the purposed architecture. From the experimental results, while transmitting a QPSK-modulated CDMA2000 1x signal with 1.2288 Msps data rate, the transmitter achieve 48 % in drain efficiency, 47 dB in ACPR, and 6 % in EVM at the output power ranging from 10 to 22 dBm.

Les problématiques d'intégrabilité et de consommation des circuits sont au centre des spécifications des émetteurs pour la téléphonie mobile. L'architecture polaire est une alternative intéressante aux architectures cartésiennes pour réduire la consommation, la surface et la pollution de l'amplificateur de puissance (PA) sur la boucle à verrouillage de phase (PLL). Néanmoins, l'évolution des nouvelles normes de téléphonie mobile est allée de pair avec un élargissement de la bande passante des modulations, ce qui peut se montré critique pour l'architecture polaire. Les travaux de cette thèse se concentrent plus particulièrement sur le chemin de phase pour des modulations larges bandes, ce dernier étant moins étudié dans la littérature que le chemin d'amplitude par le PA. La modulation de phase large bande est réalisée directement par la PLL, qui reçoit en consigne à la fois le canal à adresser et la modulation qui est insérée en 2 points de la PLL. L'architecture de la PLL peut être analogique ou numérique. Grâce à des modèles événementiels développés sous Matlab, l'étude met en évidence certains phénomènes qui ne peuvent pas être observés par des modèles linéaires largement utilisés (Laplace, transformé en « z », …). L'étude identifie notamment, pour la PLL analogique, un phénomène de mélange du bruit avec la modulation dégradant fortement la qualité du signal. Ce travail propose une méthode de dimensionnement des filtres de modulation et de la fréquence de référence de la PLL pour résoudre ce problème. Pour la PLL numérique, un autre phénomène est identifié et amène à insérer la modulation en 3 points de la PLL. Finalement, une méthode de dimensionnement des banques de capacités dédiées à la modulation sur l'oscillateur est proposée. / Power consumption and integration are two key challenges of today mobile transmitter, especially for mobile phone applications. The polar architecture is an interesting alternative to classic architectures in order to reduce the power consumption, the silicon area and the pollution from the PA to the PLL. Unfortunately, the communication standards evolution such as LTE goes with a modulation bandwidth enlargement. This becomes critical for the use of polar architecture. Contrary to amplitude modulation done through the PA, phase modulation path through the PLL is less covered in literature. This phase modulation path which can be either analog or digital is the purpose of this work. Thanks to nonlinear event-driven models developed with Matlab, it has been possible to show some phenomenon which cannot be observed with widely used linear models (in Laplace or z-domain). For instance, in the fractional-N PLL, a mixing between the noise and the modulation signal strongly degrades the modulation performance. A method combining PLL sizing and modulation filtering is proposed to solve this issue. For the digital PLL, TDC gain estimation has a big impact on the EVM (Error Vector Magnitude) for wideband modulations and a solution is proposed which consists of converting the classical two-point modulator into a three-point modulator. Finally, an oscillator's capacitors banks sizing dedicated to the modulation is proposed.