Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters. Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis. VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept. CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented. VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control. CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage. / Ph. D.

As 3G handset manufacturers add more and more features such as multimedia applications, color displays, video cameras, web browsing, gaming, WLAN, and MP3 players, the current consumption of a handset is ever increasing. Of the many components, the RF power amplifiers receive the most attention as they draw significant battery current and continue to represent the largest power load on the battery. In order to improve the overall efficiency of a power amplifier, it is important to know the operating uplink transmit power levels of a mobile phone in the WCDMA network. The work in this thesis makes two major contributions. First is the characterization of uplink transmit power in WCDMA networks based on current network data (collected in AT&T's WCDMA network) and realistic usage scenarios. Second is an investigation of the relationship between the battery life and the probability distribution function of the transmit power. Another important finding is that the talk time estimates using field tests, lab testing and theoretical expressions all give results to within 5%. Based on these data, design goals for WCDMA power amplifiers (in order to improve the talk times significantly) are suggested. The output power levels where the PA efficiencies have to be improved in order to significantly increase the battery life of WCDMA handsets are presented. / Master of Science

The conventional power factor correction circuit has a fixed output voltage. However, in some applications, a PFC circuit with a wide output voltage range is needed. A single phase power factor correction circuit with wide output voltage range is developed in this work. After a comparison of two main power stage candidates (Buck+Boost and Sepic) in terms of efficiency, complexity, cost and device rating, the buck+boost converter is employed as the variable output PFC power stage. From the loss analysis, this topology has a high efficiency from light load to heavy load. The control system of the variable output PFC circuit is analyzed and designed. Charge average current sensing scheme has been adopted to sense the input current. The problem of high input harmonic currents at low output voltage is discussed. It is found that the current loop gain and cross over frequency will change greatly when the output voltage changes. To solve this problem, an automatic gain control scheme is proposed and a detailed circuit is designed and added to the current loop. A modified input current sensing scheme is presented to overcome the problem of an insufficient phase margin of the PFC circuit near the maximum output voltage. The charge average current sensing circuit will be bypassed automatically by a logical circuit when the output voltage is higher than the peak line voltage. Instead, a resistor is used to sense the input current at that condition. Therefore, the phase delay caused by the charge average current sensing circuit is avoided. The design and analysis are based on a novel air conditioner motor system application. Some detailed design issues are discussed. The experimental results show that the variable output PFC circuit has good performance in the wide output voltage range, under both the Boost mode when the output voltage is high and the Buck+Boost mode when the output voltage is low. / Master of Science

The power consumption of smart camera in car black box varies significantly between light load and heavy load. The high efficiency voltage regulator is necessary in prolong the life of smart camera battery. Since the smart camera only recording the video when car is driving, the most time of the smart camera works in the sleep mode. Hence the light load efficiency is important in this application, however, conventional buck converter usually have high efficiency at heavy load but poor efficiency at light load. To increase the light load efficiency of buck converter, this research continues Yeago's two phase buck converter with optimum phase selection control and Zhao's two mode buck converter to further improve the light load efficiency for the target application. With 5V input voltage and 1.2V output voltage, the proposed two-mode synchronous buck converter can supply the load power from 12mW to 1.44W. To improve the light load efficiency of conventional buck converter, the proposed design applied Wei's baby buck concept to provide another light load power stage to reduce the switching loss and driving loss at light load. Then, the variable frequency ripple-based constant on-time control with discontinuous conduction mode (DCM) in light load is applied to the baby-buck mode to reduce the switching frequency to further reduce the switching loss. Also, the baby-buck mode uses the synchronous buck topology to remove the diode in asynchronous converter to increase the efficiency at light load. Finally, a sensorless mode selector remove the sensing resistor in power stage to increase the efficiency for entire load range, especially for the heavy load. The mode selector can select the optimum mode for different load condition, and the opposite mode would completely shut down to save the loss. The proposed design is implement in CMOS 0.25um technology. The proposed monolithic buck converter which include the power stage of heavy buck mode, baby-buck mode and the controller is fabricated. The measurement result shows the close loop efficiency varies from 70%-83% toward the entire load range. / Master of Science

With the use of the simplistic equivalent circuits, loss mechanism in conventional power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate drive circuits is analyzed. Resonant gate drive techniques are investigated and a new resonant gate drive circuit is presented. The presented circuit adds minor complexity to conventional gate drivers but reduces the MOSFET gate drive loss very effectively. To further expand its use in driving Half-Bridge MOSFETs, another circuit is proposed in this thesis. The later circuit simplifies the isolation circuitry for the top MOSFET and meanwhile consumes much lower power than conventional gate drivers. / Master of Science

In modern power electronics systems there is a growing trend to replace discrete devices with integrated power electronic modules (IPEMs). In this way, several components can be replaced by a single component. By using prefabricated building blocks, the engineer simplifies the design process, reducing the total design cycle time and cost. By integrating only the necessary components to provide power switching, the end user has a pre-optimized building block with the flexibility to be used in a large variety of applications. Besides simplifying the design process, power modules should be designed in such a way as to improve the performance of the power converter. This begs the question as to how best to judge if one IPEM has better performance than another or better performance than its discrete counterpart. In analyzing a converter's performance, popular criteria include efficiency, power density, device stresses, and EMI. All of these criteria are strongly linked to the switching characteristics of the IPEM's power devices. This thesis is a comprehensive study of the requirements for obtaining and analyzing the switching characteristics of the IPEM's power devices. It outlines the important switching characteristics and the implications of each characteristic on converter performance. It deals with the relevant measurement issues, specifically addressing the minimum requirements, which sensors are most suitable, and problems leading to inaccurate data. A parametric study is conducted to determine the effects of several circuit and operating parameters on the switching characteristics. Using the resulting data and the knowledge from the measurement study, we can decide how to design the testbed layout, what operating conditions should be chosen for testing, and what effects of the tester must be decoupled to truly see the effects of IPEM design. The thesis concludes with the design of standard test equipment and procedures. / Master of Science

Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress. For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFETs (30 V breakdown voltage) in series are simulated in a chopper circuit. The drain-source voltage sharing in switching off-mode shows that the devices can share voltage within their breakdown ranges. The switching characteristics are studied, and the switching energy losses without parasitic inductance and with 5 nH parasitic inductances are 203.38 µJ and 316.49 µJ, respectively. The critical parasitic inductance is the one connecting the source of the upper MOSFET and the drain of the middle MOSFET. The switching energy loss due to critical parasitic inductance is about 44.4% of the total switching energy loss. The layout is designed for the double-substrates direct-bond module and wire-bonded module using direct-bond-copper (DBC) substrate. Based on layout dimensions and packaging materials, the packaging module's parasitic parameters are obtained using Ansoft® Q3D extractor. Using parasitic inductance values from simulation, the switching energy losses of direct-bond module and wire-bonded module are 296.18 µJ and 238.99 µJ, respectively. Thermal management is then studied using Ansoft® ePhysics. The MOSFET junction-to-air thermal resistances of the double-substrate direct-bond module and the single-substrate wire-bonded module are 33oC/W and 82oC/W, respectively. Hence, by comparing the direct-bond module with a wire-bonded power module, direct-bond module shows lower parasitic impedances and better thermal management. To test the breakdown voltage of series-connected power MOSFETs module, three TI DualCoolTM N-channel NexFET Power MOSFETs (25 V breakdown voltage) in series are assembled using flip-chip direct-bond technology. Three samples are assembled and the breakdown voltages are measured by using high-power curve tracer as 76 V, 82 V, and 72 V. The more accurate method for testing breakdown voltages by digital voltmeter obtains 77.51 V, 82.31 V, and 73.06 V. The series-connected power MOSFETs module shows compact volume, low parasitic impedances, thermal resistances and improved breakdown voltage. This power module has strong potential for use in applications that require minimized packaging size and parasitic inductance for high voltage, high switching frequency, and high efficiency. / Master of Science

Master of Science / Department of Statistics / Leigh W. Murray / The term retrospective power describes methods for estimating the true power of a test after data have been collected. These methods have been recommended by some authors when null hypothesis of a test cannot be rejected. This report uses simulations to study power as a construct of an observed effect, variance, sample size, and set level of significance under the balanced one-way analysis of variance model for normally distributed populations with constant variance. Retrospective power, as a construct of sample data, is not recommended when the null hypothesis of a test cannot be rejected. When the p-value of the test is large, estimates for true power tend to fall below the 0.80 level and width-minimized confidence limits for true power tend to be wide.

In order to satisfy the huge demand energy transmission in future, the DC grid concept is proposed based on voltage sourced converter (VSC) HVDC and modular multilevel converter (MMC) HVDC technologies. It provides an attractive approach for long distance power transmission such as offshore renewable energy transmission in Europe. However, there are two main obstacles in the DC grid development. The first obstacle is the DC fault detection and selective isolation. Under severe fault condition, the DC grid is desired to isolate the healthy and faulty part which implies the whole grid system will operate normally during the fault. The second obstacle is the voltage stepping in DC grid system. The high power converter is desired to achieve high voltage stepping ratio yet must be cost-effective. In this thesis, an IGBT-based DC/DC converter employing an internal inductor-capacitor-inductor (LCL) passive circuit is presented to overcome above two obstacles. The proposed converter can achieve high voltage stepping without internal AC transformer implying smaller converter size and it is also designed to have reasonable efficiency in high power application. In addition, the converter has good response even under extreme fault conditions. The IGBT-based LCL DC/DC converter design procedure and performance under fault condition is investigated based on the theoretical studies initially. The converter is modelled on PSCAD platform under normal/fault operation and the simulation results are used for converter efficiency calculation and fault analysis. The advantages of IGBT-based LCL DC/DC converter are demonstrated by comparing with other two high power DC/DC converter topologies. A low power level prototype of LCL DC/DC converter is built following the design principle. The hardware results are used to verify the theoretical conclusions. The VSC converter is defenceless to DC faults in DC grid application. In order to overco The VSC converter is defenceless to DC faults in DC grid application. In order to overcome this major drawback, a fault tolerant VSC converter employing LCL passive circuit is studied in this thesis. The LCL VSC converter design principle is presented by analysing the converter equations. The converter model is developed on PSCAD platform under normal/fault operation. An advanced control method is designed based on developed MATLAB analytical model to improve the LCL VSC converter stability. The advantages of LCL VSC converter are presented by comparing with its performance with conventional L-VSC converter considering efficiency and fault response. A fault tolerant DC grid topology employing LCL VSCs and using low speed protection is also investigated in this thesis. The simple mechanical DC circuit breakers are used at DC bus bars and at connecting points of each DC cable. A comprehensive protection scenario including DC cable differential protection, DC bus bar protection and back up protection is employed to protect the whole DC grid against any probable DC faults. An accurate DC cable model is adopted for a four-terminal DC grid which is modelled on PSCAD platform. The advantage and feasibility of this method in DC fault protection is investigated based on the developed grid model.

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