In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigation of several integratable lateral power devices. Lateral power devices are used in power IC designs because of their compatibility with analog & digital IC process. To obtain devices with high current density, large safe operating area, fast response and low cost is highly desirable for power ICs. In Part II of this thesis, several lateral power devices are discussed and simulated, including lateral IGBT, lateral MCT and double gate lateral MCTs. It is shown that lateral IGBT and lateral MCTs are good candidates for power IC applications. / Master of Science

As wearable technology and wireless sensor nodes become more and more ubiquitous, the batteries required to power them have become more and more unappealing as they limit lifetime and scalability. Energy harvesting from body heat provides a solution to these limitations. Energy can be harvested from body heat using thermoelectric generators, or TEGs. TEGs provide a continuous, scalable, solid-state energy source ideal for wearable and wireless electronics and sensors. Unfortunately, current TEG technology produces low power (< 1 mW) at a very low voltage (20-90 mV) and require the load to be matched to the TEG internal resistance for maximum power transfer to occur. This thesis research proposes a power management integrated circuit (PMIC) that steps up ultralow voltages generated by TEGs to a regulated 3 V, while matching the internal resistance. The proposed boost converter aims to harvest energy from body heat as efficiently and flexibly as possible by providing a regulated 3 V output that can be used by a variable load. A comparator-based burst mode operation affords the converter a high conversion ratio at high efficiency, while fractional open circuit voltage maximum power point tracking ensures that the controller can be used with a variety of TEGs and TEG setups. This control allows the converter to boost input voltages as low as 50 mV, while matching a range of TEG internal source resistances in one stage. The controller was implemented in 0.25 µm CMOS and taped out in February 2016. Since these fabricated chips will not be completed and delivered until May 2016, functionality has only been verified through simulation. Simulation results are promising and indicate that the peak overall efficiency is 81% and peak low voltage, low power efficiency is 73%. These results demonstrate the the proposed converter can achieve overall efficiencies comparable to current literature and low power efficiencies better than similar wide range converters in literature. / Master of Science

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第14628号 / 工博第3096号 / 新制||工||1460(附属図書館) / 26980 / UT51-2009-D340 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 鈴木 実, 教授 藤田 静雄 / 学位規則第4条第1項該当