This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail. We examine the design of TIMR as well as the implementation and considerations. We propose a number of control schemes that range from traditional DVFS to "race to sleep". This thesis also shows simulations of the technique using a existing voltage regulator in order to find the time and energy overhead of implementing the design. We find a 100μs switching time delay and 118μJ energy overhead associated with changing the voltage rail. This work concludes with comparisons to current energy saving techniques. / Graduation date: 2012

Many methods for EMI suppression have been developed in the last fifty years, most of them, showing a hardly change in its implementation. Traditional tools for EMI suppression are related to the use of filters, shielding techniques and new methods for layout improvement. These hardware techniques are normally supported with waveform shapes having themselves a lower spectral content. This kind of signals makes part of a different concept of EMI suppression that consists of limiting the spectral content in the signal itself. When possible, just waveforms with a lower spectral content should be used, this way making easier, simpler and cheaper the use of filters and other suppression means. In this line, EMI-reduction techniques such a Spread Spectrum Clock Generation (SSCG) are contributing to eliminate or limit the problem at the root, that is, at the signal itself.This thesis is developed in several parts, corresponding to different chapters. A summary of these chapters is presented onwards:After introduction in chapter 1, a wide theoretical development of the modulation and related concepts are presented in chapter 2. It is explained generically all aspects related to the modulation and particularly, to the frequency modulation. Main parameters of frequency modulation are presented and explained in detail and how practical considerations may affect to the theoretical behaviour of these parameters. Because the theoretical part of this thesis is completely based on the fundamentals of Fourier Transform, a sufficient explanation was thought to include for its right understanding . Finally, all this knowledge is summarized in a computational algorithm (MATLAB environment), capable of generating any frequency modulation of a sinusoidal carrier and the corresponding spectral components resulting from the modulation process.Chapter 3 takes profit of the results obtained in Chapter 2 where it is possible to obtain the theoretical behaviour of the different modulation profiles of interest: sinusoidal, triangular, exponential and mixed waveforms. This way, chapter 3 is intended to completely understand and analyze the theoretical behaviour of these modulation profiles and be quantified according to several significant measure parameters. Afterwards, a comparison of these modulation profiles is carried out by means of the measure parameters defined previously. A proposal of control for a real power converter and theoretical considerations to apply a certain SSCG method to switching power converters are also included in this chapter. After all aspects of frequency modulation by means of SSCG methods have been theoretically developed, it is mandatory the verification of the theoretical conclusions through an experimental test plant. Chapter 4 starts with the description, theoretical calculation and physical implementation of this test plant. Most practical considerations are here dealt with, like the influence of the Spectrum Analyzer's Resolution Bandwidth (RBW) on the measured EMI, a proposal of a practical method to select a valuable SSCG technique applied to Switching Power Converters, comparative measurements of conducted EMI within the range of conducted emissions (0 Hz 30 MHz) and a proposal about SSCG as a method to avoid interfering a certain signal.Chapter 5 summarizes the whole conclusions gathered through the previous chapters and, finally, chapter 6 lists references related to the thesis, separated into different thematic groups.

Modern arc welding machines utilize controllable high frequency DC/DC power supply with high dynamic and steady state current regulation performance. In the design robustness, small size and low weight, low complexity, and high efficiency are the defining criteria. The most suitable approach for a 5 kW arc welding machine power supply application is the high frequency Full-Bridge Phase-Shifted Zero Voltage Switching (FB-PS-ZVS) DC/DC converter with an isolation transformer. This converter not only gives the advantage of zero voltage switching for a wide load current range, it also provides reduced Electromagnetic Interference (EMI) and reduced component stress compared to standard PWM converters. In this thesis a FB-PS-ZVS DC/DC converter with 5 kW power rating is designed for modern arc welding machine applications. IGBTs are utilized at 50 kHz switching frequency for high efficiency and control bandwidth. The output current of the DC/DC converter is controlled via a Digital Signal Processor (DSP) control platform. The performance of the designed DC/DC converter is evaluated via the computer simulations and the experimental study of the constructed prototype.

In this thesis a multifunctional DC/DC converter board will be developed for utilization as an educational experiment set in the switched-mode power conversion laboratory of power electronic courses. The board has a generic power-pole structure allowing for easy configuration of various power converter topologies and includes buck, boost, buck-boost, flyback, and forward converter topologies. All the converters can be operated in the open-loop control mode with a switching frequency range of 30-100 kHz and a maximum output power of 20 W. Also the buck converter can be operated in voltage mode control and the buck-boost converter can be operated in peak-current-mode control for the purpose of demonstrating the closed loop control performance of DC/DC converters. The designed board allows for experimentation on the DC/DC converters to observe the macroscopic (steadystate/ dynamic, PWM cycle and low frequency) and microscopic (switching dynamic) behavior of the converters. In the experiments both such characteristics can be clearly observed such that students at basic learning level (involving only the macroscopic behavior), and students at advanced learning level (additionally involving the parasitic effects) can benefit from the experiments. The thesis reviews the switch mode conversion principles, gives the board design and proceeds with the experiments illustrating the capabilities of the experimental system.

Power has become an important design closure parameter in today’s ultra low submicron digital designs. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters or voltage regulators design, system, board and package thermal analysis, power grid design and signal integrity analysis to minimizing power itself. This work focuses on challenges arising due to increase in power to power grid design and analysis. Challenges arising due to lower geometries and higher power are very well researched topics and there is still lot of scope to continue work. Traditionally, designs go through average IR drop analysis. Average IR drop analysis is highly dependent on current dissipation estimation. This work proposes a vector less probabilistic toggle estimation which is extension of one of the approaches proposed in literature. We have further used toggles computed using this approach to estimate power of ISCAS89 benchmark circuits. This provides insight into quality of toggles being generated. Power Estimation work is further extended to comprehend with various state of the art methodologies available i.e. spice based power estimation, logic simulation based power estimation, commercially available tool comparisons etc. We finally arrived at optimum flow recommendation which can be used as per design need and schedule. Today’s design complexity – high frequencies, high logic densities and multiple level clock and power gating - has forced design community to look beyond average IR drop. High rate of switching activities induce power supply fluctuations to cells in design which is known as instantaneous IR drop. However, there is no good analysis methodology in place to analyze this phenomenon. Ad hoc decoupling planning and on chip intrinsic decoupling capacitance helps to contain this noise but there is no guarantee. This work also applies average toggle computation approach to compute instantaneous IR drop analysis for designs. Instantaneous IR drop is also known as dynamic IR drop or power supply noise. We are proposing cell characterization methodology for standard cells. This data is used to build power grid model of the design. Finally, the power network is solved to compute instantaneous IR drop. Leakage Power Minimization has forced design teams to do complex power gating – multilevel MTCMOS usage in Power Grid. This puts additonal analysis challenge for Power Grid in terms of ON/OFF sequencing and noise injection due to it. This work explains the state of art here and highlights some of the issues and trade offs using MTCMOS logic. It further suggests a simple approach to quickly access the impact of MTCMOS gates in Power Grid in terms of peak currents and IR drop. Alternatively, the approach suggested also helps in MTCMOS gate optimization. Early leakage optimization overhead can be computed using this approach.

Power supply noise, which is the variation in the supply voltage across the on-die supply terminals of VLSI circuits, is a serious performance degrader in digital circuits and mixed analog-digital circuits. In digital VLSI systems, power supply noise causes timing errors such as delays, jitter, and false switching. In microprocessors, power supply noise reduces the maximum operating frequency (FMAX) of the CPU. In mixed analog-digital circuits, power supply noise manifests as the substrate noise and impairs the performance of the analog portion. The decrease in the available noise margin with the decrease in the feature size of transistors in CMOS systems makes the power supply noise a very serious issue, and demands new methods to reduce the power supply noise in sub-micron CMOS systems. In this thesis, we develop a new method to determine optimal time-delays between the switching of input/output (I/O) data buffers in digital VLSI systems that realizes maximum reduction of the power supply noise. We first discuss methods to characterize the distributed nature of the Power Delivery Network (PDN) in the frequency-domain. We then develop an analytical method to determine the optimal delays using the frequency-domain response of the PDN and the supply current spectrum of the buffer units. We explain the mechanism behind the cancellation of the power supply noise by the introduction of optimal buffer-to-buffer delays. We also develop a numerical method to determine the optimal delays and compare it with the analytical method. We illustrate the reduction in the power supply noise by applying the optimal time-delays determined using our methods to two examples of PDN. Our method has great potential to realize maximum reduction of power supply noise in digital VLSI circuits and substrate noise in mixed analog-digital VLSI circuits. Lower power supply noise translates into lower cost and improved performance of the circuit.

Ein wirtschaftlich optimal ausgelegtes Magnetschwebebahnsystem kann zur Lösung der weltweit drohenden Verkehrsprobleme beitragen, die im Zuge von Globalisierung und steigender Bevölkerung vor allem Regionen mit hohem Wachstumspotential bevorstehen. Im Grenzbereich zwischen Technikbewertung und Wirtschaftlichkeitsbetrachtung werden in der vorliegenden Forschungsarbeit einerseits Optimierungsansätze für das Subsystem „Antrieb und Energieversorgung“ des Transrapid vorgestellt. Sie leisten einen Beitrag zur Erhöhung der Wirtschaftlichkeit des Gesamtsystems über den Lebenszyklus. Auf der anderen Seite wird eine Methodik präsentiert, die es ermöglicht, die betriebswirtschaftlichen Wirkungen der einzelnen Optimierungsmaßnahmen für das Gesamtsystem abzuschätzen. Ausgangspunkt der Untersuchungen ist die Analyse von Zielsystem und aktuellem Entwicklungsstand des Transrapid-Systems. Darauf aufbauend lassen sich mögliche Optimierungsschwerpunkte für das Teilsystem „Antrieb und Energieversorgung“ ableiten und Varianten in Abhängigkeit der Auslegungsparameter erstellen. Kernstück der vorliegenden Ausarbeitung ist die Erstellung einer Optimierungsstrategie, die eine makroskopische Bewertung der Optimierungsansätze ermöglicht. Dies ist erforderlich, da sämtliche Optimierungen stark divergierende Auswirkungen auf die Betriebswirtschaftlichkeit des Gesamtsystems haben - neben den Kosten werden über die Leistungsfähigkeit auch die Erlöse eines Projekts beeinflusst. Basis der Strategie ist die Verknüpfung von Kostenänderungsfaktoren mit Leistungsfähigkeitsparametern. Infolgedessen wird im Ergebnis der Arbeit ein Werkzeug geschaffen, das unter projektspezifischen Randbedingungen als Entscheidungshilfe zur Auslegung des Transrapid-Subsystems „Antrieb und Energieversorgung“ dient.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The goal of this dissertation is to evaluate the effectiveness of model predictive control (MPC) for a magnetically suspended flywheel energy storage uninterruptible power supply (FlyUPS). The reason this research topic was selected was to determine if an advanced control technique such as MPC could perform better than a classical control approach such as decentralised Proportional-plus-Differential (PD) control. Based on a literature study of the FlyUPS system and the MPC strategies available, two MPC strategies were used to design two possible MPC controllers were designed for the FlyUPS, namely a classical MPC algorithm that incorporates optimisation techniques and the MPC algorithm used in the MATLAB® MPC toolbox™. In order to take the restrictions of the system into consideration, the model used to derive the controllers was reduced to an order of ten according to the Hankel singular value decomposition of the model. Simulation results indicated that the first controller based on a classical MPC algorithm and optimisation techniques was not verified as a viable control strategy to be implemented on the physical FlyUPS system due to difficulties obtaining the desired response. The second controller derived using the MATLAB® MPC toolbox™ was verified to be a viable control strategy for the FlyUPS by delivering good performance in simulation. The verified MPC controller was then implemented on the FlyUPS. This implementation was then analysed in order to validate that the controller operates as expected through a comparison of the simulation and implementation results. Further analysis was then done by comparing the performance of MPC with decentralised PD control in order to determine the advantages and limitations of using MPC on the FlyUPS. The advantages indicated by the evaluation include the simplicity of the design of the controller that follows directly from the specifications of the system and the dynamics of the system, and the good performance of the controller within the parameters of the controller design. The limitations identified during this evaluation include the high computational load that requires a relatively long execution time, and the inability of the MPC controller to adapt to unmodelled system dynamics. Based on this evaluation MPC can be seen as a viable control strategy for the FlyUPS, however more research is needed to optimise the MPC approach to yield significant advantages over other control techniques such as decentralised PD control. / Thesis (MIng (Computer and Electronic Engineering))--North-West University, Potchefstroom Campus, 2013