The primary advantage of Class D amplifier is high power efficiency (typically >90%). However, there are two problems in open-loop Class D design: Total Harmonic Distortion (THD) and output dc static current (the power efficiency will be degraded). The THD is rising from non-ideal sample carrier in Pulse Width Modulation circuit, and output dc static current is due to the non-match transfer characteristic in output stage. For designer to have such problems will be a large load. To improve these two problems, we proposed a Class D power amplifier with passive feedback design. Simulation and Measurement results show that the power efficiency is higher than 90% at 250Hz ~ 4KHz. Furthermore, the THD is less than 0.24% at 4 KHz in both simulation and experimental results.

abstract: Performance improvements have largely followed Moore's Law due to the help from technology scaling. In order to continue improving performance, power-efficiency must be reduced. Better technology has improved power-efficiency, but this has a limit. Multi-core architectures have been shown to be an additional aid to this crusade of increased power-efficiency. Accelerators are growing in popularity as the next means of achieving power-efficient performance. Accelerators such as Intel SSE are ideal, but prove difficult to program. FPGAs, on the other hand, are less efficient due to their fine-grained reconfigurability. A middle ground is found in CGRAs, which are highly power-efficient, but largely programmable accelerators. Power-efficiencies of 100s of GOPs/W have been estimated, more than 2 orders of magnitude greater than current processors. Currently, CGRAs are limited in their applicability due to their ability to only accelerate a single thread at a time. This limitation becomes especially apparent as multi-core/multi-threaded processors have moved into the mainstream. This limitation is removed by enabling multi-threading on CGRAs through a software-oriented approach. The key capability in this solution is enabling quick run-time transformation of schedules to execute on targeted portions of the CGRA. This allows the CGRA to be shared among multiple threads simultaneously. Analysis shows that enabling multi-threading has very small costs but provides very large benefits (less than 1% single-threaded performance loss but nearly 300% CGRA throughput increase). By increasing dynamism of CGRA scheduling, system performance is shown to increase overall system performance of an optimized system by almost 350% over that of a single-threaded CGRA and nearly 20x faster than the same system with no CGRA in a highly threaded environment. / Dissertation/Thesis / M.S. Computer Science 2011

Methods for analyzing the structural-acoustic power efficiency of active structures are developed. For this work we define the power efficiency as the ratio of the sound power radiated by a structure to the maximum possible radiated sound power. An active structure is defined as one that has electromechanical actuators distributed over its surface for the purpose of structural-acoustic excitation. The power efficiency of planar, baffled structures with arbitrary boundary conditions is examined using a combination of methods based on numerical integration, variational principles, and finite element analysis. The fundamental result of this work is that computing the power efficiency of an active structure reduces to the solution of two eigenvalue problems. The maximum possible sound power radiated by a planar, baffled structure is shown to be equivalent to the largest eigenvalue of the acoustic power transfer matrix. The structural-acoustic power efficiency is the solution of a separate generalized eigenvalue problem whose parameters include the location of the electromechanical actuators and the type of electromechanical actuation. The advantage of this metric over other measures of radiation efficiency is that 0 and 1 bound the structural-acoustic power efficiency. Furthermore, solving for the power efficiency as a function of frequency yields a measure of the bandwidth of the structural-acoustic actuator. Power efficiency is analyzed for point force actuation and distributed moment actuation. Numerical simulations demonstrate that maximizing the power efficiency requires that the magnitude and phase of the structural modal velocity vector be matched to that of the eigenvector that corresponds to the maximum eigenvalue of the acoustic power transfer matrix. Matching the modal velocity to the maximizing eigenvector produces a vibration shape that maximizes the sound power radiation of the structure. Individual actuators are not able to achieve high efficiency over a broad frequency range for both types of electromechanical actuation. Multiple-actuator arrays are able to achieve higher average efficiency at the expense of increased number of actuators. An optimization problem is then posed to maximize the structural-acoustic power efficiency by varying the location and size of distributed moment actuators. We demonstrate that an average efficiency on the order of 0.85 is possible over a large bandwidth through optimal placement and sizing of a set of four distributed moment actuators. Experimental results on a baffled plate demonstrate that correct phasing of the actuators results in velocity distributions that correlate well with predicted results. / Ph. D.

<p>Modulation of neural activity with electrical stimulation is a widespread therapy for treating neurological disorders and diseases. Two notable applications that have had striking clinical success are deep brain stimulation (DBS) for the treatment of movement disorders (e.g., Parkinson's disease) and spinal cord stimulation (SCS) for the treatment of chronic low back and limb pain. In these therapies, the battery life of the stimulators is much less than the required duration of treatment, requiring patients to undergo repeated battery replacement surgeries, which are costly and obligate them to incur repeatedly the risks associated with surgery. Further, deviations in lead position of 2-3 mm can preclude some or all potential clinical benefits, and in some cases, generate side-effects by stimulation of non-target regions. Therefore, despite the success of DBS and SCS, their efficiency and ability to activate target neural elements over non-target elements, termed selectivity, are inadequate and need improvement.</p><p>We combined computational models of volume conduction in the brain and spine with cable models of neurons to design novel electrode configurations for efficient and selective electrical stimulation of nervous tissue. We measured the efficiency and selectivity of prototype electrode designs in vitro and in vivo. Stimulation efficiency was increased by increasing electrode area and/or perimeter, but the effect of increasing perimeter was not as pronounced as increasing area. Cylindrical electrodes with aspect (height to diameter) ratios of > 5 were the most efficient for stimulating neural elements oriented perpendicular to the axis of the electrode, whereas electrodes with aspect ratios of < 2 were the most efficient for stimulating parallel neural elements.</p><p>Stimulation selectivity was increased by combining two or more electrodes in multipolar configurations. Asymmetric bipolar configurations were optimal for activating parallel axons over perpendicular axons; arrays of cathodes with short interelectrode spacing were optimal for activating perpendicular axons over parallel axons; anodes displaced from the center of the target region were optimal for selectively activating terminating axons over passing axons; and symmetric tripolar configurations were optimal for activating neural elements based on their proximity to the electrode. The performance of the efficient and selective designs was not be explained solely by differences in their electrical properties, suggesting that field-shaping effects from changing electrode geometry and polarity can be as large as or larger than the effects of decreasing electrode impedance.</p><p>Advancing our understanding of the features of electrode geometry that are important for increasing stimulation efficiency and selectivity facilitates the design of the next generation of stimulation electrodes for the brain and spinal cord. Increased stimulation efficiency will increase the battery life of IPGs, increase the recharge interval of rechargeable IPGs, and potentially reduce stimulator volume. Greater selectivity may improve the success rate of DBS and SCS by mitigating the sensitivity of clinical outcomes to malpositioning of the electrode.</p> / Dissertation

Distributed on-chip voltage regulation where multiple voltage regulators are distributed among different locations of the chip demonstrates advantages as compared to on-chip voltage regulation utilizing a single voltage regulator. Better on-chip voltage noise performance and faster transient response can be realized due to localized voltage regulation. Despite the advantages of distributed on-chip voltage regulation, unbalanced current sharing issue can occur among each voltage regulator, which has been demonstrated to deteriorate power conversion efficiency, stability, and reliability of the power delivery network. An effective balanced current sharing scheme that can be applied to most voltage regulator types is proposed to balance the current sharing. Furthermore, a relatively high on-chip temperature induced by increased power density leads to prominent voltage regulator performance degradations due to aging. The emerging type of digital low-dropout regulator is investigated regarding aging induced transient and steady state performance degradations. Reliability enhancement techniques for digital low-dropout regulators are developed and verified. Such techniques introduce negligible power and area overhead and do not affect the normal operations of digital low-dropout regulators. Reliability enhancement techniques also reduce the area overhead needed to mitigate aging induced performance degradations. Area overhead saving further translates into more space for increased number of distributed on-chip voltage regulators, enabling scalable on-chip voltage regulation.

<p>The wide spread use of IEEE Wireless LAN 802.11 in battery operated mobile devices introduced the need of power consumption optimization while meeting Quality-of-Service (QoS) requirements of applications connected through the wireless network. The IEEE 802.11 standard specifies a baseline power saving mechanism, hereafter referred to as standard Power Save Mode (PSM), and the IEEE 802.11e standard specifies the Automatic Power Save Delivery (APSD) enhancement which provides support for real-time applications with QoS requirements. The latest amendment to the WLAN 802.11 standard is the IEEE 802.11n standard which enables the use of much higher data rates by including enhancements in the Physical and MAC Layer. In this thesis, different 802.11n MAC power saving and QoS optimization possibilities are analyzed comparing against existing power saving mechanisms.</p><p>Initially, the performance of the existing power saving mechanisms PSM and Unscheduled-APSD (UAPSD) are evaluated using the 802.11n process model in the OPNET simulator and the impact of frame aggregation feature introduced in the MAC layer of 802.11n was analyzed on these power saving mechanisms. From the performance analysis it can be concluded that the frame aggregation will be efficient under congested network conditions. When the network congestion level increases, the signaling load in UAPSD saturates the channel capacity and hence results in poor performance compared to PSM. Since PSM cannot guarantee the minimum QoS requirements for delay sensitive applications, a better mechanism for performance enhancement of UAPSD under dynamic network conditions is proposed.</p><p>The functionality and performance of the proposed algorithm is evaluated under different network conditions and using different contention settings. From the performance results it can be concluded that, by using the proposed algorithm the congestion level in the network is reduced dynamically thereby providing a better power saving and QoS by utilizing the frame aggregation feature efficiently.</p>

Demand for high data rates is increasing rapidly for the future wireless generations, due to the requirement ofubiquitous coverage for wireless broadband services. More base stations are needed to deliver these services, in order tocope with the increased capacity demand and inherent unreliable nature of wireless medium. However, this would directly correspond to high infrastructure costand energy consumption in cellular networks. Nowadays, high power consumption in the network is becoming a matter of concern for the operators,both from environmental and economic point of view. Cooperative communications, which is regarded as a virtual multi-input-multi-output (MIMO) channel, can be very efficient in combating fading multi-path channels and improve coverage with low complexity and cost. With its distributed structure, cooperativecommunications can also contribute to the energy efficiency of wireless systems and green radio communications of the future. Using networkcoding at the top of cooperative communication, utilizes the network resources more efficiently. Here we look at the case of large scale use of low cost relays as a way of making the links reliable, that directly corresponds to reductionin transmission power at the nodes. A lot of research work has focused on highlighting the gains achieved by using network codingin cooperative transmissions. However, there are certain areas that are not fully explored yet. For instance, the kind of detectionscheme used at the receiver and its impact on the link performance has not been addressed.The thesis looks at the performancecomparison of different detection schemes and also proposes how to group users at the relay to ensure mutual benefit for the cooperating users.Using constellation selection at the nodes, the augmented space formed at the receiver is exploited for making the links more reliable. Thenetwork and the channel coding schemes are represented as a single product code, that allows us to exploit the redundancy present in theseschemes efficiently and powerful coding schemes can also be designed to improve the link performance. Heterogeneous network deployments and adaptive power management has been used in order to reduce the overall energy consumption in acellular network. However, the distributed structure of nodes deployed in the network, is not exploited in this regard. Here we have highlightedthe significance of cooperative relaying schemes in reducing the overall energy consumption in a cellular network.  The role of differenttransmission and adaptive resource allocation strategies in downlink scenarios have been investigated in this regard.It has been observed that the adaptive relaying schemes can significantly reduce the total energy consumption as compared to the conventionalrelaying schemes. Moreover, network coding in these adaptive relaying schemes, helps in minimizing the energy consumption further.The balance between the number of base stations and the relays that minimizes the energy consumption, for each relaying scheme is also investigated. / QC 20120124

Hydraulic circuits with fast dynamic response are often characterized by low power efficiency; on the other hand, energy-efficient circuits under certain circumstances, can demonstrate slow transient responses. Continuously rising energy costs combined with the demand on high performance has necessitated that hydraulic circuits become more efficient yet still demonstrate superior dynamic response. This thesis introduces a new hydraulic circuit configuration which demonstrates high dynamic performance and high efficiency. A pump-controlled hydraulic motor system was used as the basis of the study because of its high circuit efficiency. This is primarily because there is no power loss between the pump and motor. To improve the dynamic response of the pump, a DC motor was designed to control the pump swashplate (and hence flow rate) directly. The pump and DC motor were mathematically modeled and their parameters were experimentally identified. Based on the model and experimental results, a nonlinear PID controller was designed for the DC motor. By means of the DC motors quick dynamic response (in the order of 10 ms), the DC motor controlled pump demonstrated a fast dynamic response with a rise time of 15 to 35 ms depending on the pump pressure. As the dynamic response speed of the pump flow rate was increased, overshoot of the hydraulic motor output also increased. To reduce this overshoot, a bypass flow control circuit was designed to bypass part of the flow during the transient. Due to the unique operating requirements of the bypass flow control system, a PID controller with a resetable integral gain was designed for the valve to reduce the rise time of the bypass control valve. The feasibility ("proof of concept") of the bypass flow control concept was first established using simulation techniques. The simulation results showed that the bypass flow control system could significantly reduced the overshoot of the hydraulic motor rotational speed. The bypass controller was applied to the experimental test circuit. The transient results for the pump-controlled motor system with the bypass flow control are presented under a constant resistive and an inertial load. The test results showed that the bypass flow control could reduce the overshoot of the hydraulic motor rotational speed by about 50%. The relative efficiency of the circuit with the bypass flow control system was 1% to 5% lower for the particular pump-controlled system that was used in this study. For a pump/motor that does not demonstrate significant flow ripple of the magnitude experienced in this study, the relative efficiency would be the same as the pump/motor system without bypass. It was concluded that the proposed bypass control system, combined with the DC motor-swashplate driven pump, could be used to create an energy efficient circuit with excellent dynamic transient responses.

Hydraulic circuits with fast dynamic response are often characterized by low power efficiency; on the other hand, energy-efficient circuits under certain circumstances, can demonstrate slow transient responses. Continuously rising energy costs combined with the demand on high performance has necessitated that hydraulic circuits become more efficient yet still demonstrate superior dynamic response. This thesis introduces a new hydraulic circuit configuration which demonstrates high dynamic performance and high efficiency. A pump-controlled hydraulic motor system was used as the basis of the study because of its high circuit efficiency. This is primarily because there is no power loss between the pump and motor. To improve the dynamic response of the pump, a DC motor was designed to control the pump swashplate (and hence flow rate) directly. The pump and DC motor were mathematically modeled and their parameters were experimentally identified. Based on the model and experimental results, a nonlinear PID controller was designed for the DC motor. By means of the DC motors quick dynamic response (in the order of 10 ms), the DC motor controlled pump demonstrated a fast dynamic response with a rise time of 15 to 35 ms depending on the pump pressure. As the dynamic response speed of the pump flow rate was increased, overshoot of the hydraulic motor output also increased. To reduce this overshoot, a bypass flow control circuit was designed to bypass part of the flow during the transient. Due to the unique operating requirements of the bypass flow control system, a PID controller with a resetable integral gain was designed for the valve to reduce the rise time of the bypass control valve. The feasibility ("proof of concept") of the bypass flow control concept was first established using simulation techniques. The simulation results showed that the bypass flow control system could significantly reduced the overshoot of the hydraulic motor rotational speed. The bypass controller was applied to the experimental test circuit. The transient results for the pump-controlled motor system with the bypass flow control are presented under a constant resistive and an inertial load. The test results showed that the bypass flow control could reduce the overshoot of the hydraulic motor rotational speed by about 50%. The relative efficiency of the circuit with the bypass flow control system was 1% to 5% lower for the particular pump-controlled system that was used in this study. For a pump/motor that does not demonstrate significant flow ripple of the magnitude experienced in this study, the relative efficiency would be the same as the pump/motor system without bypass. It was concluded that the proposed bypass control system, combined with the DC motor-swashplate driven pump, could be used to create an energy efficient circuit with excellent dynamic transient responses.

The wide spread use of IEEE Wireless LAN 802.11 in battery operated mobile devices introduced the need of power consumption optimization while meeting Quality-of-Service (QoS) requirements of applications connected through the wireless network. The IEEE 802.11 standard specifies a baseline power saving mechanism, hereafter referred to as standard Power Save Mode (PSM), and the IEEE 802.11e standard specifies the Automatic Power Save Delivery (APSD) enhancement which provides support for real-time applications with QoS requirements. The latest amendment to the WLAN 802.11 standard is the IEEE 802.11n standard which enables the use of much higher data rates by including enhancements in the Physical and MAC Layer. In this thesis, different 802.11n MAC power saving and QoS optimization possibilities are analyzed comparing against existing power saving mechanisms. Initially, the performance of the existing power saving mechanisms PSM and Unscheduled-APSD (UAPSD) are evaluated using the 802.11n process model in the OPNET simulator and the impact of frame aggregation feature introduced in the MAC layer of 802.11n was analyzed on these power saving mechanisms. From the performance analysis it can be concluded that the frame aggregation will be efficient under congested network conditions. When the network congestion level increases, the signaling load in UAPSD saturates the channel capacity and hence results in poor performance compared to PSM. Since PSM cannot guarantee the minimum QoS requirements for delay sensitive applications, a better mechanism for performance enhancement of UAPSD under dynamic network conditions is proposed. The functionality and performance of the proposed algorithm is evaluated under different network conditions and using different contention settings. From the performance results it can be concluded that, by using the proposed algorithm the congestion level in the network is reduced dynamically thereby providing a better power saving and QoS by utilizing the frame aggregation feature efficiently.