This thesis deals with analysis of measurement system capability in the production of rotary components from the viewpoint of operator error reduction and reliability of human factors. The aim is to carry out a literature review on the topic and then to analyze the current system in the company ZNOJEMSKÉ STROJÍRNY, s.r.o. Based on the obtained data suggest appropriate corrective arrangements to improve the current situation.

Pour les nœuds technologiques avancés, la consommation statique des circuits intégrés est devenue un facteur essentiel de l'industrie microélectronique. L'efficacité énergétique des circuits est mesurée en fonction de leur performance et en fonction de leur consommation statique. Face à l'augmentation de la variabilité des paramètres physiques et environnementaux, la technologie silicium sur isolant complètement désertée (FD-SOI : Fully-Depleted Silicon-On-Insulator) permet de prolonger la loi de Moore dans le domaine nanométrique. Dans ce mémoire une étude statistique de l'énergie des circuits intégrés CMOS-FDSOI est réalisée. Des bibliothèques statistiques qui caractérisent le délai et la puissance statique des transistors CMOS-FDSOI sont mises en place. Compte tenu des avantages liés à la technologie FDSOI, des approches statistiques basées sur les bibliothèques sont appliquées pour estimer le délai et la puissance statique. En conservant l'exactitude de l'estimation, ces approches apportent un gain important en temps CPU. Suite à l'estimation du délai et de la puissance statique, les variations énergétiques des transistors CMOS-FDSOI sont étudiées en fonction de la tension d'alimentation et en fonction de la tension de polarisation. Ainsi, grâce à la détermination d'un compromis Délai-Puissance Statique efficace et l'élaboration d'un flow d'optimisation statistique, l'énergie statique d'un circuit a pu être optimisée. / For advanced technology nodes, static consumption of integrated circuits has become a key factor for the microelectronics industry. Circuit energy efficiency is measured in terms of performance and static consumption. With the increase of physical and environmental parameters, the Fully-Depleted Silicon-on-Insulator technology allows to extend Moore's law in the nanometer domain. In this work, a statistical study of CMOS-FDSOI integrated circuit energy is carried out. Statistical libraries characterizing delay and static power of CMOS-FDSOI transistors are presented. Given the advantages of the FDSOI technology, statistical approaches based on the libraries are applied in order to estimate delay and static power. While maintaining the accuracy of the estimations, these approaches provide a significant gain in CPU time. Following delay and static power estimation, CMOS-FDSOI transistors energy variations are considered according to supply voltage and voltage body biasing. Thus, by determining an efficient Delay-Static Power compromise and the development of a statistical optimization flow, static energy of a circuit has been optimized.

Submitted by Silvana Teresinha Dornelles Studzinski (sstudzinski) on 2016-02-19T12:32:34Z No. of bitstreams: 1 Renato Luis Valente de Boer_.pdf: 1664872 bytes, checksum: aa7b8bde00fe02ba359b9222a2147fda (MD5) / Made available in DSpace on 2016-02-19T12:32:34Z (GMT). No. of bitstreams: 1 Renato Luis Valente de Boer_.pdf: 1664872 bytes, checksum: aa7b8bde00fe02ba359b9222a2147fda (MD5) Previous issue date: 2010-06-01 / Nenhuma / Este trabalho tem como tema a análise da incorporação dos efeitos variabilidade dos processos sobre o indicador IROG (Índice de Rendimento Operacional Global) e os seus desdobramentos na GPT (Gestão do Posto do Trabalho). Como objetivo principal buscou-se a proposição de um modelo para avaliação do impacto da variabilidade sobre o IROG e a GPT. O modelo proposto foi testado em duas empresas do segmento metal-mecânico, a partir do estudo de quatro postos de trabalho. Parte-se, inicialmente de uma revisão bibliográfica dos conceitos da GPT e da evolução do uso do indicador IROG na avaliação da eficiência dos equipamentos vinculada à TPM (Total Productive Maintenance); considera-se ainda, as perdas por gestão tais como: falta de programação, falta de operador, reuniões, etc. Também fizeram parte da revisão bibliográfica os conceitos relacionados à variabilidade dos processos e formas para o seu monitoramento. Com base nos estudos de caso desenvolvidos em quatro equipamentos, comprovou-se que a aplicação do modelo proposto proporcionou melhorias nos resultados do IROG. Como exemplos destes resultados citam-se: o aumento do IROG no mês dezembro de 49% para 62% no caso 1 e de 71% para 77% no caso 3. Outro resultado percebido está relacionado ao uso do modelo como ferramenta de gestão, o que proporcionou aos envolvidos na GPT, um melhor entendimento da variabilidade, a correta identificação das causas comuns e especiais de variação e, conseqüentemente, a tomada de ações apropriadas nos postos de trabalho. / This work has covered the analysis of the incorporation of the effects related to process variability on the OEE (Overall Equipment Effectiveness) Index and its consequences on WM (Workplace Management). The main objective was to propose a model for assessing the impact of variability on OEE and WM. The proposed model was tested in two metal-mechanic companies, by studying four work stations. It originally started with a review of the concepts of WM and the evolution of the use of OEE in evaluating the efficiency of equipment tied to the TPM (Total Productive Maintenance); it has been considered as well management wastes such as lack of production planning, lack of operator, meetings, etc. A review of the concepts related to the variability of processes and ways to monitor it were also taken into consideration. Based on case studies developed in four equipments, it was shown that the implementation of the proposed model provided improvements in the results of OEE. For instance: the OEE increased in last December from 49% to 62% in case 1 and from 71% to 77% in case 3. Another result is related to the perceived use of the model as a management tool, which provided for those involved in the WM a better understanding of variability, the correct identification of common and special causes of variation and, consequently, the implementation of appropriate action on the work stations.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Aim of this thesis is to analyze the current situation, to identify bottlenecks and to propose improvements to the department of acquisitions in the selected financial company, which is an important part of the Czech market and which desire not to be named. In the first part of my thesis is provided to the reader a theoretical basis necessary to understand the following text. Then I create simulation models for individual teams, which take part in the mentioned department. These models are based only on average and total values. That is why in the next section, there is described the work to bring them closer to reality with shifts of administrators and the variable number of entities, which are processed throughout the day. Based on the analysis of calculated values, I propose two methods of redistribution of actions to reduce the number of employees and to increase their efficiency.

L'ère des technologies CMOS fortement submicroniques et des circuits à hautes performances temporelles et énergétiques exige la réduction de l'impact sur les circuits : de la fluctuation du procédé de fabrication (P), de la tension d'alimentation (V) et de la température (T). Il est donc nécessaire de mettre en place des capteurs ou ring oscillateurs sur puce dédiés à la qualification intrinsèque des circuits intégrés en termes de PVT. Les capteurs seront activés pendant la phase de test des circuits ou pendant leur phase de fonctionnement normal, et les mesures seront converties en données numériques permettant de classifier les performances temporelles et énergétiques du système-sur-puce. Dans ce cadre, la présente thèse en milieu industriel a permis le développement de techniques et d'algorithmes de compensations post-fabrication en réduisant la consommation et/ou augmentant la vitesse du circuit. Précisément, les algorithmes validés au niveau silicium utilisent l'ajustement de la tension d'alimentation pour une compensation à gros-grain, ainsi que l'ajustement de la tension des substrats des transistors NMOS et PMOS pour une compensation à fin-grain. / The new requirement for nanometer CMOS technologies enabling optimal speedand power performances is to increase the integrated circuits' robustness under thefluctuation of the PVT parameters: Process (P), Voltage (V), and Temperature (T). In thisway, identifying the exact process on a die per die basis using on-chip sensors or ringoscillators becomes a necessity. This hardware (sensors) is used to measure the intrinsicperformance of the silicon either during industrial test or while applications are running. Thesensors' data are converted to a digital format in order to classify parts at the manufacturingstage (speed binning). Within this context, the present thesis has focused on the developmentof post-manufacturing compensation algorithms in order to minimise power consumptionand/or maximise speed. More precisely, the algorithms validated at the silicon level combineboth the voltage scaling for large-grain tuning, and the body biasing for fine-grain tuning.

La course à la miniaturisation des circuits électroniques pousse à développer des systèmes faible coût, quece soit en terme de consommation d’énergie ou de ressources de calcul. Il est ainsi possible de réduire la consommationen diminuant la tension d’alimentation et/ou la fréquence d’horloge, mais ceci a pour conséquence de diminuer aussila vitesse de fonctionnement du circuit. Une commande prédictive rapide permet alors de gérer dynamiquement un telcompromis, de manière à ce que la consommation d’énergie soit minimisée tout en garantissant de bonnes performances.Les stratégies de commande proposées ont notamment l’avantage d’être très robustes aux dispersions technologiquesqui sont un problème récurrent dans les nanopuces. Des solutions sont également proposées afin de réduire le coût decalcul du contrôleur. Les systèmes à échantillonnage non-uniforme, dont la loi de commande est calculée et mise à jourlorsqu’un événement est déclenché, sont ainsi étudiés. Ce principe permet de réduire le nombre d’échantillons et, parconséquent, d’économiser des ressources de calcul, tout en garantissant de bonnes performances du système commandé.Des résultats de simulation, et surtout expérimentaux, valident finalement l’intérêt d’utiliser une telle approche. / The demand of electronic components in all embedded and miniaturized applications encourages to developlow-cost components, in term of energy consumption and computational resources. Actually, the power consumption canbe reduced when decreasing the supply voltage and/or the clock frequency, but with the effect that the device runs moreslowly in return. Nevertheless, a fast predictive control strategy allows to dynamically manage this tradeoff in order tominimize the energy consumption while ensuring good performance of the device. Furthermore, the proposals are highlyrobust to tackle variability which is a real problem in nanometric systems on chip. Some issues are also suggested inthis thesis to reduce the control computational cost. Contrary to a time-triggered system where the controller calculatesthe control law at each (constant and periodic) sampling time, an event-based controller updates the control signalonly when the measurement sufficiently changes. Such a paradigm hence calls for resources whenever they are indeednecessary, that is when required from a performance or stability point of view for instance. The idea is to soften thecomputational load by reducing the number of samples and consequently the CPU utilization. Some simulation andexperimental results eventually validate the interest of such an approach.

The diploma thesis deals with usage of statistical methods to assure capability of production process. The theoretical part includes the definition of quality management, basic statistical concepts and statistical process control. The practical part presents basic information about the company P & L, spol. s r. o. and analyzes the production process of selected parts. The tools of statistical process control are applied and measures to assure capability of production process are proposed.