This study aims to design a Shunt Semi-Active Power Factor Correction Circuits , which can be applied to high power circuit by low switching frequency. The designed circuit can avoid power loss working with high switching frequency when using the method of active power factor correction .The experimental configuration based on DSP is applied to a compressor of air conditioner with varied load. The simulation check the developed circuit using Ispice . Both of the experimental and simulation results have guaranteed the derived configuration reach the expected goals.

The reluctance torque of switched reluctance motor could drive the rotor directly. Rotor doesn¡¦t need to be made from permanent magnet and the demagnetization and heat emission problems can be avoided. There are also a lot of advantages, such as the low cost, high efficiency, high stability and high hot emission, make it very attractive to the engineers and researchers. The dual-flange-pole rotor structure will induce non-linear magnetic filed in the air gap between armature and rotor, so the reluctance torque is not easy to handle. The switched reluctance motor is considered hard to control at the early stages of development. In recently years, with the rapid improvement of power electronic devices and microprocessor chips, the engineers and researchers pay more attentions to overcome the difficulties encountered in both the software and hardware step by step. It can now exert the motor¡¦s capability to contend with the inductor motor and the alternating current motor. Furthermore, it is more advantageous than others in the high energy density, high temperature and adverse circumstances. It has obviously caught caused the industry¡¦s attention and the academia's research interests. The work of this is to design and develop a drive system for the switched reluctance motor drive system by using the 32-bit floating point Digital Signal Processor, and operate it in coordination with the peripheral circuits. Finally, the study will integrate the graph control programming to design a monitoring and control system with Man-Machinery Interface (MMI) for monitoring voltage, current and speed of the switched reluctance motor drive system.

This thesis study presents design and SystemC implementation of a Crypto Processor for Advanced Encryption Standard (AES), Data Encryption Standard (DES) and Triple DES (TDES) algorithms. All of the algorithms are implemented in single architecture instead of using separate architectures for each of the algorithm. There is an Instruction Set Architecture (ISA) implemented for this Crypto Processor and the encryption and decryption of algorithms can be performed by using the proper instructions in the ISA. A permutation module is added to perform bit permutation operations, in addition to some basic structures of general purpose micro processors. Also the Arithmetic Logic Unit (ALU) structure is modified to process some crypto algorithm-specific operations. The design of the proposed architecture is studied using SystemC. The architecture is implemented in modules by using the advantages of SystemC in modular structures. The simulation results from SystemC are analyzed to verify the proposed design. The instruction sets to implement the crypto algorithms are presented and a detailed hardware synthesis study has been carried out using the tool called SystemCrafter.

A compact cryptographic processor with custom integrated cryptographic coprocessors is designed and implemented. The processor is mainly aimed for IPSec applications, which require intense processing power for cryptographic operations. In the present design, this processing power is achieved via the custom cryptographic coprocessors. These are an AES engine, a SHA-1 engine and a Montgomery modular multiplier, which are connected to the main processor core through a generic flexible interface. The processor core is fully compatible with Zylin Processor Unit (ZPU) instruction set, allowing the use of ZPU toolchain. A minimum set of required instructions is implemented in hardware, while the rest of the instructions are emulated in software. The functionality of the cryptographic processor and its suitability for IPSec applications are demonstrated through implementation of sample IPSec protocols in C-code, which is compiled into machine code and run on the processor. The resultant processor, together with the sample codes, presents a pilot platform for the demonstration of hardware/software co-design and performance evaluation of IPSec protocols and components.

In this thesis, position and current control systems for a brushless DC (Direct Current) motor are designed and integrated into one FPGA (Field Programmable Gate Array) chip. Experimental results are obtained by driving the brushless DC motors of Control Actuation System of a guided missile. Because of their high performance, brushless DC motors are widely used in Control Actuation Systems of guided missiles. In order to control the motor torque, current controller is designed and implemented in the FPGA. Position controller is designed to fulfill the position commands. A soft processor in the FPGA is used to connect and configure the current controller, position sensor interfaces and communication modules such as UART (Universal Asynchronous Receiver Transmitter) and Spacewire. In addition / position controller is implemented in the soft processor in the FPGA. An FPGA based electronic board is designed and manufactured to implement control algorithms, power converter circuitry and to perform other tasks such as communication with PC (Personal Computer). In order to monitor the behavior of the controllers in real time and to achieve performance tests, a graphical user interface is provided.

This thesis is composed of three independent parts, which are respectively focused on three different applications. 1. A Circuit Design of Fast Bipolar Inner Product Processor for Neural Associative Memory Networks¡G A novel and high-speed realization of the bipolar-valued inner product processor for associative memory networks is presented. The proposed design is verified to speed up the inner product computation compared with prior works. 2. An Area-Saving 8-bit A/D Converter Using A Binary Search Scheme¡G A fast and area-saving analog-to-digital converter using DFFs and a digital-to-analog converter is proposed. This design provides a reasonably fast solution for the embedded ADC with the area penalty growing linearly with the data length. 3. A Smart Battery Monitor Emulator System¡G An efficient smart battery monitor emulator system is designed by using the bq2018 IC of Benchmarq company. This system is aimed to improve the battery monitoring efficiency such that the exact remaining power and time of the battery can be estimated.

Due to the differences in batteries of a series-connected battery bank, the restored capacity in each battery may not be the same when being charged. In order to extend battery cycle life, the charger for the battery bank must have the capability of charging equalization. This thesis proposes a non-dissipative balance charging circuit based on buck-boost topology for a series-connected battery bank. Each battery in a battery bank is associated with a buck-boost converter. This topology can efficiently alleviate the unbalance of charge among batteries by taking off the charge from the affluently charged batteries and then allotting to those insufficient ones. To accomplish this complicated and accurate control, a digital signal processor (DSP) with sensors and interface circuits is adopted. It monitors the variations of battery voltages, activates the associated buck-boost converter, and adjusts the duty ratio of the converter to regulate the energy to be released. In virtue of the adoption of digital control kernel, the control circuit can be simple and the control flexibility can be favored. A battery bank with four series connected lead-acid batteries is used for illustrating the operating behavior and describing the operation modes of the balance charging circuit. The results of experiments convincingly advocate the applicability of the proposed approach.

The design of this thesis intends to present that 120¢X Communication and Flux-Weakening Control techniques can be successfully applied to a Digital Signal Processor (DSP) together with the hardware structure of an inverter. Experimental results are shown that utilizing IPM Motor as Drive Motor of Electric Vehicle, 120¢X Communication techniques can reduce ripple torque and maintain the stability of output torque. Furthermore, through Phase advanced control motor, it enables a higher output torque during the mid-lower speed. Using Flux-Weakening Control helps motor from higher output speed to the highest output speed. Moreover, the security of motor driver can be enhanced by designing circuit, which prevents over voltage. The function of motor driver will be better due to the decreased hardware size and increased accuracy that are the advantage of writing DSP scripts to analyze rotor speed.

Continuous improvements in semiconductor fabrication density are enabling new classes of System-on-a-Chip (SoC) architectures that combine extensive processing logic/processing with high-density memory. Such architectures are generally called Processor-in-Memory or Intelligent Memory and can support high-performance computing by reducing the performance gap between the processor and the memory. This architecture combines various processors in a single system. These processors are characterized by their computational and memory-access capabilities in performance and energy consumption. Two main problems addressed here are how to improve the performance and reduce the energy consumption of applications running on Processor-in-Memory architectures. Accordingly, a novel strategy must be developed to identify the capabilities of the different processors and dispatch the most appropriate jobs to them to exploit them fully. Accordingly, this study proposes a novel automatic source-to-source parallelizing system, called SAGE, to exploit the advantages of Processor-in-Memory architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analytical approaches. The strategy of the SAGE system, which decomposes the original program into blocks and produces a feasible execution schedule for the host and memory processors, is also investigated. Hence, several techniques including statement splitting, weight evaluation, performance scheduling and energy reduction scheduling are designed and integrated into the SAGE system to automatically transform Fortran source programs to improve the performance of the program or reduce energy consumed by the program executed on Processor-in-Memory architecture. This thesis provides detailed techniques and discusses the experimental results of real benchmarks which are transformed by SAGE system and targeted on the Processor-in-Memory architecture.

Efficient execution of scientific applications requires an understanding of how system features impact the performance of the application. Performance models provide significant insight into the performance relationships between an application and the system used for execution. In particular, models can be used to predict the relative performance of different systems used to execute an application. Recently, a significant effort has been devoted to gaining a more detailed understanding of the performance characteristics of a fusion reaction application, GYRO. GYRO is a plasma-physics application used to gain a better understanding of the interaction of ions and electrons in fusion reactions. In this thesis, we use the well-known Prophesy system to analyze and model the performance of GYRO across various supercomputer platforms. Using processor partitioning, we determine that utilizing the smallest number of processors per node is the most effective processor configuration for executing the application. Further, we explore trends in kernel coupling values across platforms to understand how kernels of GYRO interact. In this work, experiments are conducted on the supercomputers Seaborg and Jacquard at the DOE National Energy Research Scientific Computing Center and the supercomputers DataStar P655 and P690 at the San Diego Supercomputing Center. Across all four platforms, our results show that utilizing one processor per node (ppn) yields better performance than full or half ppn usage. Our experimental results also show that using kernel coupling to model and predict the performance of GYRO is more accurate than summation. On average, kernel coupling provides for prediction estimates that have less than a 7% error. The performance relationship between kernel coupling values and the sharing of information throughout the GYRO application is explored by understanding the global communication within the application and data locality.