Denna uppsats har haft examensarbetet “MPLS kontra traditionell IP-routing - enjämförelse av resursåtgång” av Sebastian Viking och Anton Öhlin som stöd. Derasarbete jämförde processoranvändning vid routing med, respektive utan, MPLS.Resultatet påvisade att MPLS gav högre processorbelastning gentemot traditionell IProuting,tvärtemot vad teorin för MPLS säger. På grund av uppenbara motsägelsermellan teori och praktik ämnade detta arbete skapa en hypotes som undersöks deduktivtmed målet att bekräfta dess utsaga: På grund av MPLS, respektive IP:s implementation iunderliggande hårdvaruarkitektur, kommer ingen märkbar skillnad iprocessorbelastning att uppvisas vid tester där en routers uppgift är att förmedla paket.Vi har därför återskapat deras tester för att verifiera äktheten i deras resultat. Resultetfrån våra egna tester visade ingen uppenbar olikhet mellan routingteknikerna IP medCEF, respektive MPLS. Presenterat resultat visar därmed på att hypotesen, som stöds avteknikernas teori, bevisats i praktiken från denna undersökning. / This paper was based on the thesis "MPLS kontra traditionell IP routing - enjämnförelse av resursåtgång" by Sebastian Viking and Anton Öhlin. Their workcompared the CPU usage when performing routing with, and without, MPLS. Theresults demonstrates that MPLS provides higher processor load over traditional IProuting, contrary to the theory of MPLS. Due to the apparent contradictions betweentheory and practice has this work intended to create a hypothesis examined deductivelywith the aim to confirm its statement: Because of MPLS, and IP's, implementation ofthe underlying hardware architecture should no noticeable difference in processor usagebe presentated at tests where a router's job is to convey the package. Therefore, we recreatedtheir tests to confirm the authenticity of their results. The results from the testsin this paper showed no significant difference between IP routing technologies withCEF, and MPLS. Presented results thus confirm the hypothesis supported by thetheories behind the techniques used.

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With the rapid growth of XML documents to serve as a popular and major media for storage and interchange of the data on the Web, there is an increasing interest in using existing traditional relational database techniques to store and/or query XML data. Since XQuery is becoming a standard XML query language, significant effort has been made in developing an efficient and comprehensive XQuery-to-SQL query processor. In this thesis, we design and implement an <em>XQuery-to-SQL Query Processor</em> based on the <em>Dynamic Intervals</em> approach. We also provide a comprehensive translation for XQuery basic operations and FLWR expressions. The query processor is able to translate a complex XQuery query, which might include arbitrarily composed and nested FLWR expressions, basic functions, and element constructors, into a single SQL query for RDBMS and a physical plan for the <em>XQuery-enhanced Relational Engine</em>. In order to produce efficient and concise SQL queries, succinct XQuery to SQL translation templates and the optimization algorithms for the SQL query generation are proposed and implemented. The preferable <em>merge-join</em> approach is also proposed to avoid the inefficient <em>nested-loop</em> evaluation for FLWR expressions. <em>Merge-join</em> patterns and query rewriting rules are designed to identify XQuery fragments that can utilize the efficient <em>merge-join</em> evaluation. Proofs of correctness of the approach are provided in the thesis. Experimental results justify the correctness of our work.

Systolic architectures are capable of achieving high throughput by maximizing pipelining and by eliminating global data interconnects. Recursive algorithms with regular data flows are suitable for systolization. The computation of multiplicative inversion using algorithms based on EEA (Extended Euclidean Algorithm) are particularly suitable for systolization. Implementations based on EEA present a high degree of parallelism and pipelinability at bit level which can be easily optimized to achieve local data flow and to eliminate the global interconnects which represent most important bottleneck in todays sub-micron design process. The net result is to have high clock rate and performance based on efficient systolic architectures. This thesis examines high performance but also scalable implementations of multiplicative inversion or field division over Galois fields <i>GF</i>(2<i>^m</i>) in the specific case of cryptographic applications where field dimension <i>m</i> may be very large (greater than 400) and either <i>m</i> or defining irreducible polynomial may vary. For this purpose, many inversion schemes with different basis representation are studied and most importantly variants of EEA and binary (Stein's) GCD computation implementations are reviewed. A set of common as well as contrasting characteristics of these variants are discussed. As a result a generalized and optimized variant of EEA is proposed which can compute division, and multiplicative inversion as its subset, with divisor in either <i>polynomial</i> or <i>triangular</i> basis representation. Further results regarding Hankel matrix formation for double-basis inversion is provided. The validity of using the same architecture to compute field division with polynomial or triangular basis representation is proved. Next, a scalable unidirectional bit serial systolic array implementation of this proposed variant of EEA is implemented. Its complexity measures are defined and these are compared against the best known architectures. It is shown that assuming the requirements specified above, this proposed architecture may achieve a higher clock rate performance w. r. t. other designs while being more flexible, reliable and with minimum number of inter-cell interconnects. The main contribution at system level architecture is the substitution of all counter or adder/subtractor elements with a simpler distributed and free of carry propagation delays structure. Further a novel restoring mechanism for result sequences of EEA is proposed using a double delay element implementation. Finally, using this systolic architecture a CMD (Combined Multiplier Divider) datapath is designed which is used as the core of a novel systolic elliptic curve processor. This EC processor uses affine coordinates to compute scalar point multiplication which results in having a very small control unit and negligible with respect to the datapath for all practical values of <i>m</i>. The throughput of this EC based on this bit serial systolic architecture is comparable with designs many times larger than itself reported previously.

Advances in configurable logic technology have permitted the development of low-cost, high-speed configurable devices, allowing one or more soft processor cores to be introduced into a configurable computing system. Soft processor cores offer logic-area savings and reduced configuration times when compared to the hardware-only implementations typically used for application specific acceleration. Programs for a soft processor core are small and simple compared to the design of a hardware core, but can leverage custom hardware within the processor core to provide greater acceleration for specific applications. This thesis presents several configurable system models, and implements one such model on a Nios Embedded Processor Development Board. A software programmable and hardware configurable lightweight processor core known as the FAST CPU is introduced. The configurable system implementation attaches several FAST CPUs to a standard Nios processor to create a system for experimentation with application specific acceleration. This system incorporating the FAST CPUs was tested for bus utilization behaviour, computing performance, and execution times for a minheap application. Experimental results are compared to the performance of a software-only solution, and also with previous research results. Experimental results verify that the theory and models used to predict bus utilization are correct. Performance testing shows that the FAST CPU is approximately 25% slower than a general purpose processor, which is expected. The FAST CPU, however, is 31% smaller in terms of logic area than the general purpose processor, and is 8% smaller than the design of a hardware-only implementation of a minheap for application specific acceleration. The results verify that it is possible to move functionality from a general purpose processor to a lightweight processor, and further, to realize an increase in performance when a task is parallelized across multiple FAST CPUs. The experimentation uses a procedure by which a set of equations can be derived for predicting bus utilization and deriving a cost-benefit curve for a coprocessing entity. They are applied to a specific system in this research, but the methods are generalizable to any coprocessing entity.

In FIPS 186-2, NIST recommends several finite fields to be used in the elliptic curve digital signature algorithm (ECDSA). Of the ten recommended finite fields, five are binary extension fields with degrees ranging from 163 to 571. The fundamental building block of the ECDSA, like any ECC based protocol, is elliptic curve scalar multiplication. This operation is also the most computationally intensive. In many situations it may be desirable to accelerate the elliptic curve scalar multiplication with specialized hardware. In this thesis a high performance elliptic curve processor is developed which is optimized for the NIST binary fields. The architecture is built from the bottom up starting with the field arithmetic units. The architecture uses a field multiplier capable of performing a field multiplication over the extension field with degree 163 in 0. 060 microseconds. Architectures for squaring and inversion are also presented. The co-processor uses Lopez and Dahab's projective coordinate system and is optimized specifically for Koblitz curves. A prototype of the processor has been implemented for the binary extension field with degree 163 on a Xilinx XCV2000E FPGA. The prototype runs at 66 MHz and performs an elliptic curve scalar multiplication in 0. 233 msec on a generic curve and 0. 075 msec on a Koblitz curve.

A vehicle that carries a person sitting in a wheelchair has been rebuilt. The original vehicle was provided with a petrol engine, hydrostatic drive and a mechanical steering rod, making it noisy and hard to maneuver. The purpose with this project was to convert the vehicle to make it more environmental and easier to drive.A new design has been proposed where an electrical drive has replaced the noisy combustion engine and an electrical motor with joystick control has replaced the manual steering. The project was divided into two parts. One mechanical part where the construction of the drive and steering were to be decided. The other part involved programming the microprocessor and implementation of all the necessary electrical for the control system of the vehicle. The rebuild of the machine to a complete electrical machine was successful and the performance is similar to the original construction but easier to drive, less noisy and more environmental.

The goal of this bachelor thesis work was to establish a cable connection between an analogue interface board, containing a 16 bit analogue to digital converter, and a DE2 board in order to allow for digital data transmission between the two boards. The DE2 board includes an FPGA which was configured to contain a Nios II softcore microprocessor for handling the tasks of reading and saving the 16 bit digital words transmitted over the cable as well as controlling the analogue to digital converter on the interface board. During the project work various tasks had to be fulfilled which included soldering the cable for parallel transmission of the 16 bit digital data words and the control signals between the boards as well as adjusting the analogue interface board with the correct voltage supplies and jumper settings. Furthermore the hardware circuit insidethe FPGA had to be configured and the program running on the Nios II processor had to be written in C language.

Choosing a right processor for an embedded application, or designing a new pro-cessor requires us to know how it stacks up against the competition, or sellinga processor requires a credible communication about its performance to the cus-tomers, which means benchmarking of a processor is very important. They arerecognized world wide by processor vendors and customers alike as the fact-basedway to evaluate and communicate embedded processor performance. In this the-sis, the benchmarking of ePUMA multiprocessor developed by the Division ofComputer Engineering, ISY, Linköping University, Sweden will be described indetails. A number of typical digital signal processing algorithms are chosen asbenchmarks. These benchmarks have been implemented in assembly code withtheir performance measured in terms of clock cycles and root mean square errorwhen compared with result computed using double precision. The ePUMA multi-processor platform which comprises of the Sleipnir DSP processor and Senior DSPprocessor was used to implement the DSP algorithms. Matlab inbuilt models wereused as reference to compare with the assembly implementation to derive the rootmean square error values of different algorithms. The execution time for differentDSP algorithms ranged from 51 to 6148 clock cycles and the root mean squareerror values varies between 0.0003 to 0.11.

FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems.