A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ¡Ó0.31 LSB, INL is about ¡Ó0.57LSB. Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW.

Thesis (M.S.) in Electrical Engineering--University of Maine, 2002. / Includes vita. Includes bibliographical references (leaves 67-68).

A improved less area 6-bit 3.3V SAR pipelined ADC is proposed. In this work, a 3-bit ADC is designed by the improved TIQ technology and flash like SAR ADC selection scheme. With the proposed TIQ method, it cancels the reference voltage generators and the backend encoders to reduce the area cost, besides the flash-like SAR ADC selection scheme makes the ADC still operate at high speed. The new 3-bit DAC in the MDAC is completed only by MOS transistors which channel widths and lengths are only adjusted to form each DAC output-voltage levels rather than using of resisters and capacitors in voltage mode. By the method, the area of the new DAC is reduced. By combining the proposed 3-bit ADC with the proposed 3-bit MDAC, an improved 6-bit ADC with less area is designed. By the TSMC 2P4M 0.35µm CMOS process, the area of the ADC is less than 0.017mm . The work shows that the power consuming is 3.77mW, the sampling rate is 160MS/S, the DNL is 0.344, and the INL is 0.74.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references and index.

Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 80-86). Also available on the World Wide Web.

No description available.

Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters. In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second- stage analog-to-digital converter. In addition, this dissertation includes circuit design techniques that provide a digital offset correction for the comparator-based two-step structure, binary-weighted switching for an R-2R digital-to-analog converter, and reference trimming for a flash analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply. The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with an ENOB of 11.4 b, which is the lowest FOM in high-resolution analog-to-digital converters having greater than an ENOB of 10 b. Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research. / Graduation date: 2012

Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 76-77). Also available on the World Wide Web.

With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always fundamental building blocks and the bottleneck in terms of power consumption in many DSP and multimedia applications. Therefore, it is crucial to minimize the power consumption of multipliers in the system for low-power VLSI design. Besides, energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size. Based on these features, this thesis presents an approach to design low-power and reconfigurable signed pipelined multipliers. The approach dynamically detects input range of the multiplier and disables the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed approach can reconfigure the output precision of the multiplier to save power consumption. We apply this approach to two architectures: array-based and Booth-based architecture. Experimental results show that the proposed array-based pipelined multiplier leads to up 47% power saving and Booth-based multiplier leads to up 30% power saving with a little additional area and delay overheads. Besides, in order to accord with the low cost and high profit-making goal of systematic products and shorten construction period, we have designed a low-power multiplier generator. User could use the user interface to configure the multiplier size, low power architecture and the precision that user need. The generator will create the hardware architecture of low-power multiplier automatically.

No description available.