abstract: ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator. / Dissertation/Thesis / M.S. Electrical Engineering 2012

A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas dessas aplicações requerem processamento em tempo real e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. Também, a tarefa de projetar operadores morfológicos manualmente para uma dada aplicação não é trivial na prática. A programação genética, que é um ramo relativamente novo em computação evolucionária, está se consolidando como um método promissor em aplicações envolvendo processamento de imagens digitais. Seu objetivo primordial é descobrir como os computadores podem aprender a resolver problemas sem, no entanto, serem programados para essa tarefa. Essa área ainda não foi muito explorada no contexto de construção automática de operadores morfológicos. Assim, neste trabalho, desenvolve-se e implementa-se uma arquitetura original, de baixo custo, reconfigurável por meio de instruções morfológicas e lógicas geradas automaticamente através de uma aproximação linear baseada em programação genética, visando-se o processamento morfológico de imagens em tempo real utilizando FPGAs de alta complexidade, com objetivos de filtragem, reconhecimento de padrões e emulação de filtros desconhecidos de softwares comerciais, para citar somente algumas aplicações. Exemplos de aplicações práticas envolvendo imagens binárias, em níveis de cinza e coloridas são fornecidos e seus resultados são comparados com outras formas de implementação. / Mathematical morphology supplies powerful tools for low level image analysis, with applications in robotic vision, visual inspection, medicine, texture analysis and many other areas. Many of the mentioned applications require dedicated hardware for real time execution. The task of designing manually morphological operators for a given application isnot always a trivial one. Genetic programming is a relatively new branch of evolutionary computing and it is consolidating as a promising method for applications of digital image processing. The main objective of genetic programming is to discover how computers can learn to solve problems without being programmed for that. In the literature little has been found about the automatic morphological operators construction using genetic programming. In this work, the development of an original reconfigurable architecture using logical and morphological instructions generated automatically by a linear approach based on genetic programming is presented. The developed architecture is based on Field Programmable Gate Arrays (FPGAs) and has among the possible applications, image filtering, pattern recognition and filter emulation. Binary, gray level and color image practical applications using the developed architecture are presented and the results are compared with other implementation techniques.

With the advent of mass-market consumer multicore processors, the growing trend in the consumer off-the-shelf general purpose processor industry has moved away from increasing clock frequency as the classical approach for achieving higher performance. This is commonly attributed to the well-known problems of power consumption and heat dissipation with high frequencies and voltage. This paradigm shift has prompted research into a relatively new field of "many-core" processors, such as the Intel Single-chip Cloud Computer. The SCC is a concept vehicle, an experimental homogenous architecture employing 48 IA32 cores interconnected by a high-speed communication network. As similar multiprocessor systems, such as the Cell Broadband Engine, demonstrate a significantly higher aggregate bandwidth in the interconnect network than in memory, we examine the viability of a pipelined approach to sorting on the Intel SCC. By tailoring an algorithm to the architecture, we investigate whether this is also the case with the SCC and whether employing a pipelining technique alleviates the classical memory bottleneck problem or provides any performance benefits. For this purpose, we employ and combine different classic algorithms, most significantly, parallel mergesort and samplesort.

Increased levels of science objectives expected from spacecraft systems necessitate the ability to carry out fast on-board autonomous mission planning and scheduling. Heterogeneous radiation-hardened Field Programmable Gate Arrays (FPGAs) with embedded multiplier and memory modules are well suited to support the acceleration of scheduling algorithms. A methodology to design circuits specifically to accelerate Simulated Annealing Kernels (SAKs) in event scheduling algorithms is shown. The main contribution of this thesis is the low complexity scoring calculation used for the heuristic mapping algorithm used to balance resource allocation across a coarse-grained pipelined data-path. The methodology was exercised over various kernels with different cost functions and problem sizes. These test cases were benchedmarked for execution time, resource usage, power, and energy on a Xilinx Virtex 4 LX QR 200 FPGA and a BAE RAD 750 microprocessor.

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WCDMA is typically characterised as a system capable of providing mobile users with data rates up to 2 Mb/s and beyond. It has been termed an ultra high-speed, ultra high-capacity radio technology that will be able to carry a new range of fast, colourful media, such as colour graphics, video, animations, digital audio, Internet and e-mail that consumers will be able to access over their mobiles devices. This current study has researched on the various existing Multiuser detection (MUD) processes or proposals conducted by various research institutions around the world. It has identified the advantages that the past work offers, and it is these advantages that form the basis of the current research into the improvement techniques. The proposed Partial Parallel Pipelined Multiuser Detector (PPPMUD or P3MUD) has come about from two main flavours or directions of research. The first one seeks to promote the Soft Parallel Interference Cancellation technique as an effective bias mitigation technique. This bias occurring in the second stage decision statistics, exhibits a very harmful effect on system Bit Error Rate, (BER), particularly for large system loads. This current study goes further by carefully analysing the Soft Cancellation Factor, SCF behaviour to eventually derive and determine the optimum SCF value which exhibits positive characteristics when varied with the increasing system load (number of users). This optimum SCF value is called the universal SCF or SCFUNV, as it is theoretically supposed to perform favourably under various system loads. A favourable or acceptable performance would be characterised by low observed or measured BER during the system processing stages. A further enhancement to the operational performance of the SCFUNV algorithm is the SCFUNV Compensator, which is basically a compensation mechanism created by modelling the behaviour of the SCF values, and adjusts the SCFUNV depending on the system load, (number of simultaneous users). Thus, the SCFUNV is adaptively adjusted in order to perform acceptably under all load conditions. The second direction of research, as regards improvements in MUD techniques, involves the conventional Bit-Streaming, Pipelined Multiuser Detector. This came about due to the computational complexity as well as matrix inversions which affected earlier asynchronous multiuser detection techniques. This detector has a pipelined architecture which avoids multishot (block-based) detection and instead, processes the bits in a streaming fashion. The architecture consists of a matched filter followed by three stages of parallel interference cancellation, (PIC). This present study extends that research by outlining the advantages of incorporating the soft parallel interference cancellation technique, by way of the universal soft cancellation factor, (SCFUNV), into the conventional pipelined multiuser detector architecture to form the P3MUD architecture, which includes the compensator. The contributions of the proposed P3MUD system is that the observed BER output simulations are promising, with an observed overall decrease in the error rate for the P3MUD process, as compared to the conventional pipelined detection method. This decrease signifies an improvement offered by the proposed (P3MUD) algorithm. Further observed analysis indicates the possibility of decreasing the number of parallel interference cancellation stages from three to at least two, after the matched filter detection stage, without an observable change in system BER. Hence, the proposal of the two-stage P3MUD. / Dissertation (MEng (Electronic))--University of Pretoria, 2006. / Electrical, Electronic and Computer Engineering / unrestricted

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.