The work deals with design of novel pipelined AD converter using switched-capacitors approach.

This work deals with the influence of MDAC (multiplying DAC) resolution on basic blocks of pipelined AD converter. The MDAC was designed with 1,5 and 2,5 bits resolution structure using switched capacitor technique (SC) utilizing CMOS 0,7 m technology. Basic stages of this pipelined ADC are analyzed and compared.

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A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas dessas aplicações requerem processamento em tempo real e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. Também, a tarefa de projetar operadores morfológicos manualmente para uma dada aplicação não é trivial na prática. A programação genética, que é um ramo relativamente novo em computação evolucionária, está se consolidando como um método promissor em aplicações envolvendo processamento de imagens digitais. Seu objetivo primordial é descobrir como os computadores podem aprender a resolver problemas sem, no entanto, serem programados para essa tarefa. Essa área ainda não foi muito explorada no contexto de construção automática de operadores morfológicos. Assim, neste trabalho, desenvolve-se e implementa-se uma arquitetura original, de baixo custo, reconfigurável por meio de instruções morfológicas e lógicas geradas automaticamente através de uma aproximação linear baseada em programação genética, visando-se o processamento morfológico de imagens em tempo real utilizando FPGAs de alta complexidade, com objetivos de filtragem, reconhecimento de padrões e emulação de filtros desconhecidos de softwares comerciais, para citar somente algumas aplicações. Exemplos de aplicações práticas envolvendo imagens binárias, em níveis de cinza e coloridas são fornecidos e seus resultados são comparados com outras formas de implementação. / Mathematical morphology supplies powerful tools for low level image analysis, with applications in robotic vision, visual inspection, medicine, texture analysis and many other areas. Many of the mentioned applications require dedicated hardware for real time execution. The task of designing manually morphological operators for a given application isnot always a trivial one. Genetic programming is a relatively new branch of evolutionary computing and it is consolidating as a promising method for applications of digital image processing. The main objective of genetic programming is to discover how computers can learn to solve problems without being programmed for that. In the literature little has been found about the automatic morphological operators construction using genetic programming. In this work, the development of an original reconfigurable architecture using logical and morphological instructions generated automatically by a linear approach based on genetic programming is presented. The developed architecture is based on Field Programmable Gate Arrays (FPGAs) and has among the possible applications, image filtering, pattern recognition and filter emulation. Binary, gray level and color image practical applications using the developed architecture are presented and the results are compared with other implementation techniques.

<p>FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. </p><p>The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. </p><p>The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems.</p>

<p>In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.</p><p>In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB.</p><p>The design is simulated in UMC 0.18um technology in Cadence environment. The choice of technology is made as the target application for the ADC, 'X-ray Detector System' is designed in the same technology. The simulation results obtained in-term of ENOB and power consumption are satisfactory for the target application.</p>

In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort. In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB. The design is simulated in UMC 0.18um technology in Cadence environment. The choice of technology is made as the target application for the ADC, 'X-ray Detector System' is designed in the same technology. The simulation results obtained in-term of ENOB and power consumption are satisfactory for the target application.

FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems.

Due to the rapid advancement of VLSI technology, functions of multimedia systems (e.g. MP3, image processing etc,) become more complex nowadays. Therefore, more complicated system architecture and powerful computing ability are required to attain real-time process. In order to fulfill the requirement of cost and efficiency, multimedia systems usually consist of processors, ASICs and other various components. Diverse real-time functions of multimedia system can be implemented via co-operation of these components. However, these components have the differences in area, efficiency, and cost. Accordingly, it is necessary to establish a useful method and tool to decide better system architecture. ¡@¡@The main objective of the thesis is to develop a decision tool of system architecture. Given the system specification and constraints of a multimedia system, it can quickly decide a good system architecture to satisfy the constraints in accordance with the system specification . Except for partitioning various functions and mapping functions to hardware components, the decision tool must implement scheduling and pipelining to fulfill resource constraints and reach the real-time requirement. A great deal of time and cost for implementing the multimedia system can be reduced by careful scheduling and pipelining. Besides, owing to the pressure of time to market in system development, we propose a series of design flow to speed up the design process. All decision tasks in the flow are finished by automatic or semi-automatic method to reduce the exhaustion of manpower and time. Finally, we make experiments with the proposed tool on several multimedia systems. The results show that the automatic process can conform to constraints which set up by system specifications and ensure the accuracy of the process.