Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs. / Graduation date: 2011

Indiana University-Purdue University Indianapolis (IUPUI) / In this thesis, we describe a different implementation for in loop filtering method for 3D-HEVC. First we propose the use of adaptive loop filtering (ALF) technique for 3D-HEVC standard in-loop filtering. This filter uses Wiener–based method to minimize the Mean Squared Error between filtered pixel and original pixels. The performance of adaptive loop filter in picture based level is evaluated. Results show up to of 0.2 dB PSNR improvement in Luminance component for the texture and 2.1 dB for the depth. In addition, we obtain up to 0.1 dB improvement in Chrominance component for the texture view after applying this filter in picture based filtering. Moreover, a design of an in-loop filtering with Fast Bilateral Filter for 3D-HEVC standard is proposed. Bilateral filter is a filter that smoothes an image while preserving strong edges and it can remove the artifacts in an image. Performance of the bilateral filter in picture based level for 3D-HEVC is evaluated. Test model HTM- 6.2 is used to demonstrate the results. Results show up to of 20 percent of reduction in processing time of 3D-HEVC with less than affecting PSNR of the encoded 3D video using Fast Bilateral Filter.

Current trends on video technologies and services are demanding higher bit rates, highervideo resolutions and better video qualities. This issue results in the need of a new generationof video coding techniques to increase the quality and compression rates of previous standards.Since the release of HEVC, ITU-T VCEG and ISO/IEC MPEG have been studying the potentialneed for standardization of future video coding technologies with a compression capability thatsignificantly exceeds the ones from current standards. These new e↵orts of standardization andcompression enhancements are being implemented and evaluated over a software test modelknown under the name of Joint Exploration Model (JEM). One of the blocks being explored inJEM is an Adaptive Loop Filter (ALF) at the end of each frame’s processing flow. ALF aimsto minimize the error between original pixels and decoded pixels using Wiener-based adaptivefilter coefficients, reporting, in its JEM’s implementation, improvements of around a 1% in theBD MS-SSIM rate. A lot of e↵orts have been devoted on improving this block over the pastyears. However, current ALF implementations do not consider the potential use of adaptive QPalgorithms at the encoder. Adaptive QP algorithms enable the use of di↵erent quality levels forthe coding of di↵erent parts of a frame to enhance its subjective quality.In this thesis, we explore potential improvements over di↵erent dimensions of JEM’s AdaptiveLoop Filter block considering the potential use of adaptive QP algorithms. In the document, weexplore a great gamut of modification over ALF processing stages, being the ones with betterresults (i) a QP-aware implementation of ALF were the filter coefficients estimation, the internalRD-optimization and the CU-level flag decision process are optimized for the use of adaptiveQP, (ii) the optimization of ALF’s standard block activity classification stage through the useof CU-level information given by the di↵erent QPs used in a frame, and (iii) the optimizationof ALF’s standard block activity classification stage in B-frames through the application of acorrection weight on coded, i.e. not predicted, blocks of B-frames. These ALF modificationscombined obtained improvements of a 0.419% on average for the BD MS-SSIM rate in the lumachannel, showing each modification individual improvements of a 0.252%, 0.085% and 0.082%,respectively. Thus, we concluded the importance of optimizing ALF for the potential use ofadaptive-QP algorithms in the encoder, and the benefits of considering CU-level and frame-levelmetrics in ALF’s block classification stage. / Utvecklingen inom video-teknologi och service kräver högre bithastighet, högre videoupplösningoch bättre kvalitet. Problemet kräver en ny generation av kodning och tekniker för att ökakvaliteten och komprimeringsgraden utöver vad tidigare teknik kunnat prestera. Sedan lanseringenav HEVC har ITU-T VCEG och ISO/IEC MPEG studerat ett eventuellt behov av standardiseringav framtida video-kodings tekniker med kompressions kapacitet som vida överstigerdagens system. Dessa försök till standardisering och kompressionsframsteg har implementeratsoch utvärderats inom ramen för en mjukvara testmodell som kallas Joint Exploration Model(JEM). Ett av områdena som undersöks inom ramen för JEM är adaptiva loopfilter (ALF) somläggs till i slutet av varje bilds processflöde. ALF har som mål att minimera felet mellan originalpixel och avkodad pixel genom Wiener-baserade adaptiva filter-koefficienter. Mycket kraft harlagts på att förbättra detta område under de senaste åren. Men, nuvarande ALF-appliceringbeaktar inte potentialen av att använda adaptiva QP algoritmer i videokodaren. Adaptiva QPalgoritmer tillåter användningen av olika kvalitet på kodning av olika delar av bilden för attförbättra den subjektiva kvaliteten.I föreliggande uppsats kommer vi undersöka den potentiella förbättringen av JEM:s adaptivaloopfilter som kan uppnås genom att använda adaptiva QP algoritmer. I uppsatsen kommervi undersöka ett stort antal modifikationer i ALF:s process-stadier, för att ta reda på vilkenmodifikationer som har bäst resultat: (i) en QP-medveten implementering av ALF där filterkoefficientensuppskattning av den interna RD-optimeringen och CU-nivåns flaggbeslutsprocessär optimerade för användnngen av adaptiv QP, (ii) optimeringen av ALF:s standard blockaktivitets klassificerings stadie genom användning av CU-nivå-information producerad av deolika QP:n som används i en bild, och (iii) optimeringen av ALF:s standard block aktivitetsklassificerings stadier i B-bilders genom applicering av en korrektursvikt i tidigare kod, d.v.sej förutsedda, block av B-bilder. När dessa ALF modifikationer kombinerades förbättradesi genomsnitt BD MS-SSIM hastigheten i luma kanalen med 0.419%, där varje modifikationförbättrade med 0.252%, 0.085% och 0.082% var. Därigenom drog vi slutstatsen att det är viktigtatt optimera ALF för det potentiella användandet av adaptiva QP-algoritmer i kodaren, ochfördelarna av att beakta CU-nivåmätningar och bild-nivåmätningar i ALF:s block klassificeringsstadie.

The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency synthesizer module hardware. The last part of the work deals with practical implementation, verification of function and measurement of achieved parameters and their evaluation.