In this work, the circuit implementation of the front-end for Frequency Domain (FD) Sampling Receiver is presented. Shooting for two different applications, two transconductance amplifiers are designed. A high linear transconductance amplifier with 25 dBm IIP3 is proposed to form the high resolution and high sampling rate FD receiver. The whole system achieves an overall sampling rate of 2 Gs/s and resolution of 10 bits. Another low noise transconductance amplifier exploiting noise cancelling is designed to build up the FD wireless communication receiver, which is an excellent candidate for Software Define Radio (SDR) and Cognitve Radio (CR). The proposed noise cancelling scheme can suppress both thermal noise and flicker noise at the frontend. The system Noise Figure (NF) is improved by 3.28 dB. The two transconductance amplifiers are simulated and fabricated with TI 45nm CMOS technology.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.