Aim of this master’s thesis is create universal converter communication protocols. This converter will be instrumental towards testing attendance single communication protocol on microprocessors FREESCALE. Test instrument is behind purpose ease testing software PROCESSOR EXPERT. Processor expert is extended software for CODEWARRIROR. Test instrument is connected over interface USB to personal computer. PC is used like evolution tool for testing single periphery. Device could be used in future for other peripheries.

This thesis deals with the current state of development of active lower limb prostheses and focuses mainly on own design of active prostheses. The introduction deals with the anatomy of lower limb and briefly describes the walk cycle. In other chapters are summarized amputation techniques in the lower limb, followed by a description of the allocation of prostheses according to the level of amputation, which were described in earlier chapters. The thesis also deals with the division of prostheses according to the patient's activity level and briefly describes the structural differences in these individual cases. Chapter describing the actual development in the field of active prostheses initiates part dealing with the detailed description of the part of the prosthesis. The following chapters deal with the design and implementation of a prototype of active transfemoral prosthesis. The penultimate chapter deals with the software description of all parts of the prosthesis. This chapter is followed by an evaluation of the achieved results.

Emerging mobile platforms integrate heterogeneous, multicore processors to efficiently deal with the heterogeneity of data (in magnitude, type, and quality). The main goal is to achieve a high degree of energy-proportionality which corresponds with the nature and fluctuation of mobile workloads. Most existing power and energy consumption analyses of these architectures rely on simulation or static benchmarks neither of which truly reflects the type of workload the processors handle in reality. By contrast, we generate two types of stochastic workloads and employ four types of dynamic voltage and frequency scaling (DVFS) policies to investigate the energy proportionality and the dynamic power consumption characteristics of a heterogeneous processor architecture when operating in different configurations. The analysis illustrates, both qualitatively and quantitatively, that knowledge of the statistics of the incoming workload is critical to determine the appropriate processor configuration.

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Published Article / This study evaluated the difficulty, in terms of usability, of upgrading from one version of a word processor user interface (Microsoft Word 2003) to another (2007). Laboratory-based usability testing involving 23 participants, who had never used Microsoft Word 2007 before, was conducted. All participants used the two versions in a repeated-measures experimental design. A Tobii 1750 Eye Tracker was used for screen recordings during testing. Participants were also required to fill in user satisfaction questionnaires. Results from the usability test showed that, in terms of usability, migrating from an original interface to a completely changed user interface is not easy.

The prevalence of multi-core processors with recent advancement in virtualization technologies has enabled horizontal and vertical scaling within a physical node achieving economical sharing of computing infrastructures as computing clouds. Through hardware virtualization, consolidated servers each with specific number of core allotment run on the same physical node in dedicated Virtual Machines (VMs) to increase overall node utilization which increases profit by reducing operational costs. Unfortunately, despite the conceptual simplicity of vertical and horizontal scaling in virtualized cloud environments, leveraging the full potential of this technology has presented significant scalability challenges in practice. One of the fundamental problems is the performance unpredictability in virtualized cloud environments (ranked fifth in the top 10 obstacles for growth of cloud computing). In this dissertation, we present two case studies in vertical and horizontal scaling to this challenging problem. For the first case study, we describe concrete experimental evidence that shows important source of performance variations: mapping of virtual CPU to physical cores. We then conduct an experimental comparative study of three major hypervisors (i.e., VMware, KVM, Xen) with regard to their support of n-tier applications running on multi-core processor. For the second case study, we present empirical study that shows memory thrashing caused by interference among consolidated VMs is a significant source of performance interference that hampers horizontal scalability of an n-tier application performance. We then execute transient event analyses of fine-grained experiment data that link very short bottlenecks with memory thrashing to the very long response time (VLRT) requests. Furthermore we provide three practical techniques such as VM migration, memory reallocation, soft resource allocation and show that they can mitigate the effects of performance interference among consolidate VMs.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Navigation is the means by which a craft is given guidance from one known location to another. Since the global positioning system (GPS) is very accurate positioning system, a personal navigation system based on GPS is very effective. From the user point of view, the function of this system is to provide real-time positioning and timing data to the user. The system consists of 6-channel GPS oncore receiver, a system controller & processor (SC&P) card, a programmable liquid crystal display (LCD) and a keyboard. The 6-channel GPS OEM card receives GPS signal from six different satellites at a time. After processing the received GPS signal, it gives the result & status message to its output port in a typical data format. The system controller & processor card receives this message from the GPS OEM card and extracts the useful positioning & timing information in binary form. After that it processes the data and displays it on the LCD display. The keyboard has used to select the desired positioning & timing information on the display.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes the new Telemetry Processor Hardware (TPH) that Avtec Systems has developed for the Deep Space Network (DSN) Telemetry Processor (TLP) system. Avtec is providing the Telemetry Processor Hardware to RTLogic! for integration into the Telemetry Processor system. The Deep Space Network (DSN) is an international network of antennas that supports interplanetary spacecraft missions for exploration of the solar system and the universe. The Jet Propulsion Laboratory manages the DSN for NASA. The TLP system provides the capability to acquire, process, decode and distribute deep space probe and Earth orbiter telemetry data. The new TLP systems will be deployed at each of the three deep-space communications facilities placed approximately 120 degrees apart around the world: at Goldstone, California; near Madrid, Spain; and near Canberra, Australia. The Telemetry Processor Hardware (TPH) supports both CCSDS and TDM telemetry data formats. The TPH performs the following processing steps: soft-symbol input selection and measurement; convolutional decoding; routing to external decoders; time tagging; frame synchronization; derandomization; and Reed-Solomon decoding. The TPH consists of a VME Viterbi Decoder/MCD III Interface board (VM-7001) and a PCI-mezzanine Frame Synchronizer/Reed-Solomon Decoder (PMC- 6130-J) board. The new Telemetry Processor Hardware is implemented using the latest Field Programmable Gate Array (FPGA) technology to provide the density and speed to meet the current requirements as well as the flexibility to accommodate processing enhancements in the future.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes a PC-based Advanced Telemetry Processing and Display System (ATPDS)- a highend, real-time telemetry processing and display system implemented on a COTS PC platform. for A network-centric architecture was chosen from candidate architectures as the most viable for the ATPDS. The network-centric architecture is Windows NT-based, client/server based, supporting clients and servers on both local or remote PC workstations. The architecture supports distributing processing loads across multiple workstations, optimizing mission processing requirements. The advantage of this system is its flexibility and expandability with low acquisition and life-cycle support costs. The ATPDS allows the user to configure one or more small systems into a larger high-end system based on varying mission requirements.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / Measurement of vibration and acoustic signals at various locations in the launch vehicle is important to establish the vibration and acoustic environment encountered by the launch vehicle during flight. The vibration and acoustic signals are wideband and require very large telemetry bandwidth if directly transmitted to ground. The DSP based Signal Processing Unit is designed to measure and analyse acoustic and vibration signals onboard the launch vehicle and transmit the computed spectrum to ground through centralised baseband telemetry system. The analysis techniques employed are power spectral density (PSD) computations using Fast Fourier Transform (FFT) and 1/3rd octave analysis using digital Infinite Impulse Response (IIR) filters. The programmability of all analysis parameters is achieved using EEPROM. This paper discusses the details of measurement and analysis techniques, design philosophy, tools used and implementation schemes. The paper also presents the performance results of flight models.