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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
151

Optimal Design of Sensor Parameters in PLC-Based Control System Using Mixed Integer Programming

OKUMA, Shigeru, SUZUKI, Tatsuya, MUTOU, Takashi, KONAKA, Eiji 01 April 2005 (has links)
No description available.
152

Upprustning och modernisering av kraftstation vid Årbols såg och kvarn

Axelsson, Per, Hedlund, Christoffer January 2003 (has links)
No description available.
153

Adaptive multilevel quadrature amplitude radio implementation in programmable logic

Aspel, Daniel T 29 April 2004 (has links)
Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more robust physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in burst mode, and can reliably synchronize to different QAM constellations burst-by-burst. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers.
154

An Emulator for OpenGL ES 2.0 based on C-language Compiler

Tsai, Feng-wen 29 July 2008 (has links)
OpenGL ES 2.0 is the newest 3D graphics technology for hand-held devices established by Khronos. Users need a shading language compiler and a graphics card which is supportive for OpenGL ES 2.0 to develop their application on OpenGL ES 2.0. Without a graphcis processing unit and a corresponding compiler, one can not develop a 3D graphics application based on OpenGL ES 2.0. In order to solve these problems, we proposed an emulator for OpenGL ES 2.0 based on C-language compiler. The proposed emulator applies C-language compiler and CPU to fulfill the specification of OpenGL ES 2.0. With the proposed emulator, application developers can develop a 3D graphics application for OpenGL ES 2.0 without a specific hardware and a corresponding compiler and hardware designers also can compare and debug when designing their own graphics processing unit.
155

A Verilog 8051 soft core for FPGA applications

Rangoonwala, Sakina. Kougianos, Elias, January 2009 (has links)
Thesis (M.S.)--University of North Texas, August, 2009. / Title from title page display. Includes bibliographical references.
156

Efficient elliptic curve processor architectures for field programmable logic

Orlando, Gerardo. January 2002 (has links)
Thesis (Ph. D.)--Worcester Polytechnic Institute. / Keywords: computer arithmetic; elliptic curves; cryptography. Includes bibliographical references (p. 299-305).
157

Source level debugging of circuits synthesized from high level language descriptions /

Hemmert, Karl S., January 2004 (has links) (PDF)
Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 143-149).
158

Acceleration of streaming applications on FPGAs from high level constructs

Mitra, Abhishek. January 2008 (has links)
Thesis (Ph. D.)--University of California, Riverside, 2008. / Includes abstract. Title from first page of PDF file (viewed March 8, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 150-168). Also issued in print.
159

Testing and evaluation of the configurable fault tolerant processor (CFTP) for space-based application /

Hulme, Charles A. January 2003 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.
160

Designing, debugging, and deploying configurable computing machine-based applications using reconfigurable computing application frameworks /

Slade, Anthony Lynn, January 2003 (has links) (PDF)
Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2003. / Includes bibliographical references (p. 229-232).

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