Thesis--Auburn University, 2010. / Abstract. Includes bibliographic references (p.162-167).

The Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) has opened new doors as an emerging technology with high potential to replace traditional CMOS-based memory technology. This has come true due to the density, speed and non- volatility that have been demonstrated. The STT-MRAM uses Magnetic Tunnel Junction (MTJ) elements as non-volatile memory storage devices because of the recent discovery of spin-torque phenomenon for switching the magnetization states. The magnetization of the free layer in STT-MRAM can be switched from logic "1" to logic "0" by the use of a spin-transfer torque. However, the STT-MRAMs have till now only been used as universal memory. As a result, STT-MRAMs are not yet commercially used as computing elements, though they have the potential to be used as Logic-In-Memory computation applications. In order to advance this STT-MRAM technology for computation, we have used different MRAM devices that are available as memory elements with different geometries, to use it as computing elements. This dissertation presents design and implementation of such devices using different multilayer magnetic material stacks for computation. Currently, the design of STT-MRAMs is limited to only memory architectures, and there have been no proposals on the viability of STT-MRAMs as computational devices. In the present work, we have developed a design, which could be implemented for universal logic computation. We have utilized the majority gate architecture, which uses the magneto-static interaction between the freelayers of the multilayer nanomagnets, to perform computation. Furthermore, the present work demonstrates the study of dipolar interaction between nanomagnetic disks, where we observed multiple magnetization states for a nanomagnetic disk with respect to its interaction energy with its neighboring nanomagnets. This was achieved by implementing a single layer nanomagnetic disk with critical dimension selected from the phase plot of single domain state (SDS) and vortex state (VS). In addition, we found that when the interaction energy between the nanomagnetic disks with critical dimension decreases (increase in center-to-center distance) the magnetization state of the nanomagnetic disks changes from single domain state to vortex state within the same dimension. We were able to observe this effect due to interaction between the neighboring nanomagnets. Finally, we have presented the design and implementation of a Spin-Torque driven Re- configurable Array of Nanomagnets (STRAN) that could perform Boolean and non-Boolean computation. The nanomagnets are located at every intersection of a very large crossbar array structure. We have placed these nanomagnets in such a way that the ferromagnetic free layers couple with each other. The reconfigurable array design consists of an in-plane (IP) free layer and a fixed polarizer [magnetized out-of-plane (OP)]. The cells that need to be deselected from the array are taken to a non-computing oscillating state.

The movement to smart mobile connected devices which consolidate functions of traditionally separate devices is driving innovation in System-on-chips (SoCs). One of the innovations helping to meet the current needs of SoCs is the integration of larger memory with the processor, and with this, comes the challenge of testing all the memory cells. The programmable memory BIST offers a flexible approach to designers and testers because it allows the memory test algorithms to be updated when new memory fault models are discovered. But this flexibility comes as a trade-off to area as the BIST circuitry needs to be integrated next to the memory array. This report proposes enhancements to an existing design that will improve flexibility by enhancing the address generation schemes while simultaneously eliminating the need for an auxiliary memory in cases where a Type-1 NPSF background will be used. A comparison of the base design to the proposed design shows the address and data generation improvements can be achieved with only 1.8% increase in area with an 8KB memory. / text

abstract / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

This work addresses neural and analog computation on reconfigurable mixed-signal platforms. Many engineered systems could gain tremendous benefits by emulating neural systems. For example, neural systems are incredibly power efficient and fault-tolerant. They are also capable of types of computation that we cannot yet match with conventional computers. Neuromorphic engineers typically implement neural computation using analog circuits because they are low-power and naturally model some aspects of neurobiology. One problem with analog circuits is that they are typically inflexible. To address this shortcoming, our lab has developed reconfigurable analog systems known as Field Programmable Analog Arrays (FPAAs). This dissertation consists of two main parts. The first is the implementation of neural and analog circuits on FPAAs. We first implemented an adaptive winner-take-all circuit, which could model attention in neural systems. Next, we modeled the dendrite, which is the conductive tissue that relays inputs from synapses to the neuron cell body. We also implemented a subtractive music synthesizer, perhaps providing the electronic music synthesis community with a good platform for experimentation. Finally, we conducted a number of neural learning experiments on a neuromorphic platform. The second part of this dissertation includes design aspects of new FPAAs, including configurable blocks that can be used as current-mode DACs in a digitally-enhanced FPAA, the RASP 2.9v. We also consider the design of a new neuromorphic platform containing 256 neurons and over 200,000 synapses, many with learning capability. We also created an active delay line that could be used for beamforming or FIR filter applications. In summary, this work adds to the field of reconfigurable systems by both showing how to implement circuits with them and creating new systems based on lessons learned while working with previous systems.

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FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.

This master‘s final paper describes JTAG (boundary scan) interface in which discuss IEEE standart 1149.1 circuit model and the main TAP (Test Access Port) controllers instructions. Accomplished programmable integral logical ICs overview: development, leading manufacturer (ALTERA, XILINX, ACTEL) production and programmable equipment evaluation. Represented recomendation, how we can pick suitable programmable logical device. The paper presents detailed describe searching ICs family XC9500 characteristic, features and merits. In general terms presented programmable logic language VHDL value. It also produces some detailed compose describes of the project, using methods of circuit drawing and VHDL language. Master‘s hypothesis that if we will use JTAG interface processed logical programmable instrumentation in our projects we can save up time, area and improve their quality is confirmed. This is prospective technology which also soon will be in use in Lithuania.

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