Cette thèse contribue à une approche formelle de conception d'un programme de contrôle/commande pour les systèmes automatisés de production (SAP) contrôlés par des automates programmables industriels (API). Dans ce contexte, deux constats principaux ont été soulevés : il existe manque de méthodologie efficace pour la conception d'un programme API dans le monde industriel et les méthodes formelles issues du monde académique ne sont ni connues ni utilisées par l'industrie car trop complexes. Par ailleurs, l'industrie du futur nécessitera des contrôleurs toujours plus flexibles et fiables. La flexibilité implique que les programmes seront encore plus difficiles à réaliser, et par conséquent, la difficulté pour garantir la fiabilité de ceux-ci sera accrue.Pour répondre à ces problématiques, une méthode de conception formelle s'intégrant dans un cycle de développement industriel classique (cycle en V) a été proposée. De plus, afin de faciliter le transfert vers l'industrie tant d'un point de vue technique (API) qu’humain (pratique des automaticiens), le formalisme utilisé est entièrement basé sur des variables et des équations logiques appelées contraintes logiques. Ces contraintes logiques permettent la spécification des exigences informelles recensées dans le cahier des charges. A partir de ces contraintes logiques, un algorithme de résolution des contraintes, implémentable dans un API, est synthétisé et implémenté automatiquement dans un langage de programmation normalisé pour API. Ce filtre logique peut être utilisé pour : commander un SAP contrôlé par un API, vérifier formellement un programme API, mettre en sécurité un programme API déjà existant présentant des erreurs.Les travaux de cette thèse ont eu pour objectif de lever certains verrous et de globalement améliorer et renforcer l'approche par filtre logique. Dans le but de généraliser l'approche par filtre, un effort important a été réalisé autour de la formalisation des contraintes logiques et des différentes fonctions et propriétés associées au filtre logique. Cet apport de formalisation a permis, en particulier, de proposer une approche de vérification formelle de la notion de cohérence d'un filtre logique ainsi qu'une condition nécessaire et suffisante à cette propriété. Enfin, après avoir mis à jour l'algorithme d'implémentation classique, deux algorithmes de recherche locale d'une solution basés sur des techniques de solveur SAT ont été proposés. / This thesis contributes to a formal approach to design control/command program for automated production systems controlled by Programmable Logical Controller (PLC). In this context, two main observations have been highlighted: there is a lack of efficient methodology for the design of PLC program in the industrial field and the academicals formal approaches are neither known nor used in manufacturing industry due to high complexity. Furthermore, the industry of future will require flexible and reliable PLC program. The flexibility implies that programs will be even more difficult to design and, consequently, the complexity to guarantee the reliability will be increased.To address these issues, a formal design approach, presented as a classical V-cycle, have been proposed. Moreover, to facilitate the industrial transfer from both technical (PLC) and human (engineer practice) point of view, the formalism is exclusively based on logical variables and equations called logical constraints. These constraints are used to specify the informal requirements described in the specification book. From these constraints, a logical filter is synthesized automatically and a solving algorithm, IEC 61131-3 compliant, is implemented in the PLC program. This logical filter may be used to: command an automated production system controlled by a PLC, verify formally a PLC program, and make safe an existing PLC program containing errors.The contributions of this thesis covered the whole development cycle: formal specification, formal analysis and synthesis, automatic implementation in a PLC program. To support these contributions, a significant effort was made on the formalism based on logical constraints. This new formalism has allowed, in particular, to propose a necessary and sufficient condition to the coherence property of a logical filter and to guarantee the convergence of the online solving algorithm. At least, the classical solving algorithm has been updated according to the new formalism, and two algorithms based on SAT solver techniques and local research have been proposed and tested on real PLC.

With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 134-144). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--Ohio University, August, 1999. / Title from PDF t.p.

Zugl.: Hamburg, Techn. Univ., Diss., 2008

Thesis (M.S.)--Ohio University, August, 1998. / Title from PDF t.p.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2008. / Includes bibliographical references (leaves 335-340). Also available online.

Les réseaux sur puce (NoC pour «network on chip») sont des infrastructures de communication extensibles qui autorisent le parallélisme dans la communication. La conception de circuits basés sur les NoC se fait en considérant la communication et le calcul séparément, ce qui la rend plus complexe. Les outils de synthèse d'architecture (HLS pour «high level synthesis») permettent de générer rapidement des circuits performants. Mais le contrôle de ces circuits est centralisé et la communication est de type point-à-point (non extensible). Afin d'exploiter le parallélisme potentiel des algorithmes sur des FPGA dont les ressources augmentent constamment, les outils de HLS doivent extraire le parallélisme d'un programme et utiliser les ressources disponibles de manière optimisée. Si certains outils de synthèse considèrent une spécification de type flot de données, la plupart de concepteurs d'algorithmes utilise des programmes pour spécifier leurs algorithmes. Mais cette représentation comportementale doit souvent être enrichie d'annotations architecturales afin de produire en sortie un circuit optimisé. De plus, une solution complète d'accélération nécessite une intégration du circuit dans un environnement de développement, comme les GPU aujourd'hui. Un frein à l'adoption des FPGA et plus généralement des architectures parallèles, est la nécessaire connaissance des architectures matérielles ciblées.Dans cette thèse, nous présentons une méthode de synthèse qui utilise une technique d'analyse symbolique pour extraire le parallélisme d'une spécification algorithmique écrite dans un langage de haut niveau. Cette méthode introduit la synthèse de NoC pendant la synthèse d'architecture. Afin de dimensionner le circuit final, une modélisation mathématique du NoC est proposée afin d'estimer la consommation en ressources du circuit final. L'architecture générée est extensible et de type flot de données. Mais l'atout principal de l'architecture générée est son aspect programmable car elle permet, dans une certaine mesure, d'éviter les synthèses logiques pour modifier l'application / Network-on-Chip (NoC) introduces parallelism in communications and emerges with the growing integration of circuits as large designs need scalable communication architectures. This introduces the separation between communication tasks and processing tasks, and makes the design with NoC more complex. High level synthesis (HLS) tools can help designers to quickly generate high quality HDL (Hardware Description Level) designs. But their control schemes are centralized, usually using finite state machines. To take benefit from parallel algorithms and the ever growing FPGAs, HLS tools must properly extract the parallelism from the input representation and use the available resources efficiently. Algorithm designers are used with programming languages. This behavioral specification has to be enriched with architectural details for a correct optimization of the generated design. The C to FPGA path is not straightforward, and the need for architectural knowledges limits the adoption of FPGAs, and more generally, parallel architecture. In this thesis, we present a method that uses a symbolic analysis technique to extract the parallelism of an algorithmic specification written in a high level language. Parallelization skills are not required from the users. A methodology is then proposed for adding NoCs in the automatic design generation that takes the benefit of potential parallelizations. To dimension the design, we estimate the design resource consumption using a mathematical model for the NoC. A scalable application, hardware specific, is then generated using a High Level Synthesis flow. We provide a distributed mechanism for data path reconfiguration that allows different applications to run on the same set of processing elements. Thus, the output design is programmable and has a processor-less distributed control. This approach of using NoCs enables us to automatically design generic architectures that can be used on FPGA servers for High Performance Reconfigurable Computing. The generated design is programmable. This enable users to avoid the logic synthesis step when modifying the algorithm if a existing design provide the needed operators

Thesis submitted in fulfilment of the requirements for the degree Magister Technologiae: Discipline Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2008 / As one of the biggest developing country in the world, South Africa is developing very fast resent years. The country’s industrialization process is rapidly evolved. The manufacturing industry as one of the most important sections of the industrialization is playing a very heavy role in South Africa’s economic growth. Big percentage of population is involved in the manufacturing industry. It is necessary to keep and enhance the competitiveness of the South Africa’s manufacturing industry in the world wide. But the manufacturing companies are facing with unpredictable market demands and global competitions. To overcome these challenges, the manufacturing companies need to produce new products which can cater to the market demand as soon as possible. Reconfigurable Manufacturing System (RMS) is one of the possible solutions for the manufacturing companies to produce the suitable product for the market in a short period of time with low cost and flexibility. That is because the RMS can be reconfigured easily according to the required specifications for manufacturing the appropriate product for the market and with above mentioned characteristics. Now, RMS is considered as one of the promising concepts for mass production. As one of the very latest research fields, many companies, universities and institutions have been involved to design and develop RMSs. South Africa as one of the most important manufacturing country in the world, her own universities and researchers has the obligation to study this field and follow the newest development steps. In this project, a lab-scaled reconfigurable plant and a Field Programmable Gate Array (FPGA) technology based reconfigurable controller are used to realize and verify the concepts of the RMS in order to find the methodology of developing RMSs. The lab-scaled reconfigurable plant can be reconfigured into the inverted pendulum and the overhead crane. Although it is not used for manufacturing purpose, it can be used to verify the RMS concepts and the control strategies applied to it. Furthermore, control of the inverted pendulum and the overhead crane are both typical problems in the control field. It is meaningful to develop the controllers for them. As the reconfigurable plant is configured, the reconfigurable controller is reconfigured synchronously in order to produce the proper control signal for the reconfigured plant. In this project, both linear and nonlinear control strategies are deployed. Good results are received. The outcomes of the project are mainly for the education and fundamental research purposes, but the developed control strategies have significant sense towards the military missile guidance and the overhead crane operation in industry.

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