The primary issue with developing new networking protocols is testing how the protocol will behave when deployed on a large scale; of particular interest is how it will interact with existing protocols. Testing a protocol using a network simulator has drawbacks. First, the protocol must be written for the simulator and then rewritten for actual deployment. Aside from the additional work, this allows for software bugs to be introduced between testing and implementation. More importantly, there are correctness issues. Since both the new and existing protocols must be specially written for the simulator, and not actual real-world implementations, the question remains if the behavior observed and, specifically, the interactions between the protocols are valid. Direct code execution environments solve the correctness problem, but there is the loss of control that a simulator provides. Our solution is to create an environment that allows direct code execution to occur on top of a network simulator. This thesis presents the primary component of that solution: Lunar (Linux User-level Network Architecture), a user-level library that is created from the network stack portion of the Linux operating system. This allows real-world applications to link against a simulator, with Lunar serving as the bridge. For this work, an implementation of Lunar was constructed using the 2.4.3 version of the Linux kernel. Verification testing was performed to demonstrate correct functioning of the library using both TCP (including TCP with loss) and UDP. Performance testing was done to measure the overhead that Lunar adds to a running application. Overhead was measured as the percent increase in the runtime of an application with Lunar as compared to the application running without it, and ranged from approximately 2% (running over 100 Mbps switched Ethernet) to approximately 39% (1 Gbps Myrinet). / Master of Science

Modern Printed Circuit Boards (PCB) contain sophisticated and valuable electronic components, and this makes them a prime target for counterfeiting. In this thesis, we consider a method to test if a PCB is genuine. One high-level solution is to use a secret identifier of the board, together with a cryptographic authentication protocol. We describe a mechanism that authenticates all major components of PCB as part of attesting the PCB. Our authentication protocol constructs the fingerprint of PCB by extracting hardware fingerprint from the components on PCB and cryptographically combining the fingerprints. Fingerprints from each component on PCB are developed using Physical Unclonable Functions (PUF). In this thesis, we present a PUF based authentication protocol for remote integrity checking using multiple PUF component level identifiers. We address the design on 3 different abstraction levels. 1)Hardware Level, 2)Hardware Integration level, 3)Protocol level. On the hardware level, we propose an approach to develop PUF from flash memory component on the device. At the hardware Integration level, we discuss a hardware solution for implementing a trustworthy PUF based authentication. We present a prototype of the PUF based authentication protocol on an FPGA board via network sockets. / Master of Science / Electronic devices have become ubiquitous, from being used in day to day applications to device critical applications (defense, medical). These devices have valuable electronic components integrated on it. Because of its growing importance, they have attracted many counterfeiters. Counterfeiters replace a genuine component with a substandard component. In this thesis, we discuss a method to identify if an electronic device, a Printed Circuit Board in this case, is genuine. We present a solution to remotely verify authenticity of the board by extracting fingerprints from all the major components on the board. Fingerprints from each major component on the board are extracted using Physical Uncloanable Functions (PUF). These fingerprints are crypographically combined to develop an unique fingerprint for the board. Our design is addressed in 3 different abstraction levels 1) Hardware level 2) Hardware Integration level 3) Protocol level. In the Hardware level, we discuss an approach to extract fingerprints from flash memory component. In the Hardware Integration level, we discuss a hadware approach for trustworthy PUF based solution . In the Protocol level, we present a prototype of our design on FPGA using network sockets.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The design of a protocol for a satellite cluster link establishment and management that accounts for link corruption, node failures, and node re-establishment is presented in this paper. This protocol will need to manage the traffic flow between nodes in the satellite cluster, adjust routing tables due to node motion, allow for sub-networks in the cluster, and similar activities. This protocol development is in its initial stages and we will describe how we use the LabVIEW Sate Diagram tool kit to generate the code to design a state machine representing the protocol for the establishment of inter-satellite communications links.

published_or_final_version / Computer Science / Doctoral / Doctor of Philosophy

This dissertation presents measures of efficiency and locality for Internet addressing schemes. Historically speaking, many issues, faced by the Internet, have been solved just in time, to make the Internet just work~\cite{justWork}. Consensus, however, has been reached that today's Internet routing and addressing system is facing serious scaling problems: multi-homing which causes finer granularity of routing policies and finer control to realize various traffic engineering requirements, an increased demand for provider-independent prefix allocations which injects unaggregatable prefixes into the Default Free Zone (DFZ) routing table, and ever-increasing Internet user population and mobile edge devices. As a result, the DFZ routing table is again growing at an exponential rate. Hierarchical, topology-based addressing has long been considered crucial to routing and forwarding scalability. Recently, however, a number of research efforts are considering alternatives to this traditional approach. With the goal of informing such research, we investigated the efficiency of address assignment in the existing (IPv4) Internet. In particular, we ask the question: ``how can we measure the locality of an address scheme given an input AS-level graph?'' To do so, we first define a notion of efficiency or locality based on the average number of bit-hops required to advertize all prefixes in the Internet. In order to quantify how far from ``optimal" the current Internet is, we assign prefixes to ASes ``from scratch" in a manner that preserves observed semantics, using three increasingly strict definitions of equivalence. Next we propose another metric that in some sense quantifies the ``efficiency" of the labeling and is independent of forwarding/routing mechanisms. We validate the effectiveness of the metric by applying it to a series of address schemes with increasing randomness given an input AS-level graph. After that we apply the metric to the current Internet address scheme across years and compare the results with those of compact routing schemes.