abstract: CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

<p>Today, micro- and nano-electronic devices are becoming more complex and advanced as the dimensions are shrinking. It is therefore a very challenging task to develop new device technologies with performance that can be predicted. This thesis focuses on advanced measurement techniques and TCAD simulations in order to characterize and understand the device physics of advanced semiconductor devices. </p><p>TCAD simulations were made on a novel MOSFET device with asymmetric source and drain structures. The results showed that there exists an optimum range of implantation doses where the device has a significantly higher figure-of-merit regarding speed and voltage capability, compared to a symmetric MOSFET. Furthermore, both 2D and 3D simulations were used to develop a resistive model of the substrate noise coupling. </p><p>Of particular interest to this thesis is the random dopant fluctuation (RDF). The result of RDF can be characterized using very advance and reliable measurement techniques. In the thesis an ultra-high precision parametric mismatch measurement system was designed and implemented. The best ever reported performance on short-term repeatability of the measurements was demonstrated. A new bipolar parametric mismatch phenomenon was also revealed using the measurement system.</p><p>A complete simulation platform, called SiSPET (Simulated Statistical Parameter Extraction Tool), was developed and integrated into the framework of a commercial TCAD environment. A special program for randomization of the doping was developed and proven to provide RDF effects in agreement measurement. The SiSPET system was used to investigate how different device models were able to take RDF effects into account. The RDF effects were translated in to parameter fluctuations using the developed extraction routines. It was shown that the basic MOSFET fluctuation model could be improved by including the field dependenent mobility. However, if a precise description of the fluctuations is required an advanced compact-model, such as MOS Model 11 should be used.</p>

Today, micro- and nano-electronic devices are becoming more complex and advanced as the dimensions are shrinking. It is therefore a very challenging task to develop new device technologies with performance that can be predicted. This thesis focuses on advanced measurement techniques and TCAD simulations in order to characterize and understand the device physics of advanced semiconductor devices. TCAD simulations were made on a novel MOSFET device with asymmetric source and drain structures. The results showed that there exists an optimum range of implantation doses where the device has a significantly higher figure-of-merit regarding speed and voltage capability, compared to a symmetric MOSFET. Furthermore, both 2D and 3D simulations were used to develop a resistive model of the substrate noise coupling. Of particular interest to this thesis is the random dopant fluctuation (RDF). The result of RDF can be characterized using very advance and reliable measurement techniques. In the thesis an ultra-high precision parametric mismatch measurement system was designed and implemented. The best ever reported performance on short-term repeatability of the measurements was demonstrated. A new bipolar parametric mismatch phenomenon was also revealed using the measurement system. A complete simulation platform, called SiSPET (Simulated Statistical Parameter Extraction Tool), was developed and integrated into the framework of a commercial TCAD environment. A special program for randomization of the doping was developed and proven to provide RDF effects in agreement measurement. The SiSPET system was used to investigate how different device models were able to take RDF effects into account. The RDF effects were translated in to parameter fluctuations using the developed extraction routines. It was shown that the basic MOSFET fluctuation model could be improved by including the field dependenent mobility. However, if a precise description of the fluctuations is required an advanced compact-model, such as MOS Model 11 should be used.

The tri-gate FET has been hailed as the biggest breakthrough in transistor technology in the last 20 years. The increase in device performance (faster switching, less delay, improved short channel effects, etc.) coupled with the reduction in device size, would allow for huge gains in the electronics industry. This thesis aims to not only investigate the validity of these claims, but also how random dopant fluctuation (RDF) affects the tri-gates performance and how to curb these issues. In order to achieve this, an atomistic 3-D device simulation program was utilized in order to capture the many quantum mechanical effects that devices of this size experience and compare the results against a similar planar device. We see the tri-gate FET does indeed perform extremely well compared to its planar counterpart, but both devices experience a great deal of fluctuations due to the random dopants in the device. In order to limit the RDF effects a variety of methods were implemented including increasing doping concentrations in the channel, source, and drain regions, varying the source/drain junction depths, and varying the source/drain contact workfunction. The results showed that increasing doping concentrations in order to reduce the amount of space the dopants had to diffuse did not reduce the randomness experienced by the devices, but rather the randomness increased. The dopant fluctuation was insensitive to the varying of the workfunction, but was found to decrease with an increase in junction depth in the source/drain regions. With randomness in the tri-gate reduced, the overall performance should increase when used in ICs, where consistency in device characteristics is essential.

abstract: In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011