The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving towards multistandard radio, a high level of integration becomes a necessity and can only be accomplished by new improved radio architectures and full utilization of technology scaling. Modern nanometer CMOS technologies have the required performance for making high-performance RF circuits together with advanced digital signal processing. This is necessary for the development of low-cost highly integrated multistandard radios. The ultimate solution for the future is a software-defined radio, where a single hardware is used that can be reconfigured by software to handle any standard. Direct analog-to-digital conversion could be used for that purpose, but is not yet feasible due to the extremely tough requirements that put on the analog-to-digital converter (ADC). Meanwhile, the goal is to create radios that are as flexible as possible with today’s technology. The key to success is to have an RF front-end architecture that is flexible enough without putting too tough requirements on the ADC. One of the key components in such a radio front-end is a multiband multistandard low-noise amplifier (LNA). The LNA must be capable of handling several carrier frequencies within a large bandwidth. Therefore it is not possible to optimize the circuit performance for just one frequency band as can be done for a single application LNA. Two different circuit topologies that are suitable for multiband multistandard LNAs have been investigated, implemented, and measured. Those two LNA topologies are: (i) wideband LNAs that cover all the frequency bands of interest (ii) tunable narrowband LNAs that are tunable over a wide range of frequency bands. Before analog-to-digital conversion the RF signal has to be downconverted to a frequency manageable by the analog-to-digital converter. Recently the concept of direct sampling of the RF signal and discrete-time signal processing before analog-to-digital conversion has drawn a lot of attention. Today’s CMOS technologies demonstrate very high speeds, making the RF-sampling technique appealing in a context of multistandard operation at GHz frequencies. In this thesis the concept of RF sampling and decimation is used to implement a flexible RF front-end, where the RF signal is sampled and downconverted to baseband frequency. A discrete-time switched-capacitor filter is used for filtering and decimation in order to decrease the sample rate from a value close to the carrier frequency to a value suitable for analog-to-digital conversion. To demonstrate the feasibility of this approach an RF-sampling front-end primarily intended for WLAN has been implemented in a 0.13 μm CMOS process.

The ever-increasing demand for wireless throughput requires modern handset receivers to aggregate signals from multiple non-contiguously allocated RF carriers. This poses significant receiver design challenges, including concurrent signal reception, RF input interface, out-of-band (OB) linearity, and suppression of spurious responses. Commercial solutions use external antenna switches and off-chip RF multiplexers to provide non-tunable, narrowband filtering and impedance matching. The RF signal is then divided into separate signal chains, each with a dedicated receiver for signal reception. Although this solution allows the selection of any carrier combinations supported by the available RF filters, as the number of aggregation band combinations increases, the scale of the passive front-end module grows rapidly, leading to increased system complexity, extra signal loss, and degraded performance. This thesis presents the design and implementation of two receiver architectures that support reconfigurable operations and flexible, concurrent reception from two inter-band carriers with a tuned RF interface. We first present a multi-branch receiver with modulated mixer clocks (MMC). It unifies the functions of single-carrier and dual-carrier reception, as well as compressive-sampling spectrum scanning into a single architecture. With continuous-wave-modulated mixer clocks, the receiver supports concurrent reception from two distinct bands and realizes tuned impedance matching that greatly improves the OB linearity. With pseudo-noise-modulated mixer clocks, the receiver supports spectrum scanning. Disabling modulation reverts the receiver into a single-carrier receiver with good OB linearity. The 65nm CMOS prototype is developed that operates from 300 to 1300MHz and offers 2.7dB minimum NF, -1.3dBm B1dB, and +8.0dBm IIP3 for single-carrier reception. Concurrent dual-carrier reception is demonstrated that offers -8.4dBm B1dB and sub-6dB NF with the two carriers separated from 200 to 600MHz apart. For spectrum scanning, the receiver achieves a 66dB dynamic range with -75dBm sensitivity over a 630MHz RF span. In addition, a discussion of the higher-order MMC technique is included to improve the receiver’s spurious and noise performance by suppressing the higher-order responses and mitigating the noise-folding effect. Next, we present an IF-filterless, double-conversion receiver. The concurrent, narrowband RF interface is realized with two layers of passive mixing in its mixer-first branches, which translate the low-pass, baseband impedance twice to two distinct bands and improve the OB linearity. Branches with DDS-modulated LNTAs for multi-phase, switched-Gm mixing offer rejection of spurious responses and improved noise performance. The 65nm CMOS prototype is developed that operates from 100 to 1200MHz. For single-carrier reception, the receiver delivers 4.8dB minimum NF, +7.9dBm B1dB, and +22.8dBm IIP3. For concurrent signal reception, two arbitrarily-allocated RF carriers, separated from 200 to 600MHz apart, can be received concurrently. The receiver delivers a +1.9dBm B1dB and supports 8-/16-phase DDS modulation with a 30dB spurious rejection across its operating range. In addition, a theoretical study of a modified, mixer-first branch is included. By re-arranging the connections of the baseband termination resistors, the baseband noise can be fully cancelled, thus improving the receiver’s noise performance.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Multiple receiver telemetry systems are common in the aeroballistics test and evaluation community. These systems typically record telemetry data independently, requiring post-flight data processing to produce the most accurate combination of the available data. This paper addresses the issues of time synchronization between multiple data sources and determination of the best choice for each data word. Additional filtering is also developed for the case when all available data are corrupted. The performance of the proposed algorithms is presented.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / Multiple receiver telemetry systems are common in the aeroballistics test and evaluation community. These systems typically record telemetry data independently, requiring post-flight data processing to produce the most accurate combination of the available data. This paper addresses the issues of time synchronization between multiple data sources and determination of the best choice for each data word. Additional filtering is also developed for the case when all available data are corrupted. The performance of the proposed algorithms is presented.

Cheng Wang Chi. / "October 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 135-139) / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

The determination of the optimal location of transceivers is a critical design factor when deploying a wireless local area network (WLAN). The performance of the WLAN will improve in a variety of aspects when the transceivers' locations are adequately determined, including the overall cell coverage to the battery life of the client units. Currently, the most common method to determine the appropriate location of transceivers is known as a site survey, which is normally a very time and energy consuming process. The main objective of this research was to improve current methodologies for the optimal or near-optimal placement of APs in a WLAN installation. To achieve this objective, several improvements and additions were made to an existing computational tool to reflect the evolution that WLAN equipment has experienced in recent years. Major additions to the computational tool included the addition of the capability to handle multiple power levels for the transceivers, the implementation of a more adequate and precise representation of the passive interference sources for the path loss calculations, and the definition of a termination criterion to achieve reasonable computational times without compromising the quality of the solution. An experiment was designed to assess how the improvements made to the computational tool provided the desired balance between computational time and the quality of the solutions obtained. The controlled factors were the level of strictness of the termination criterion (i.e., high or low), and the number of runs performed (i.e., 1, 5, 10, 15, and 20 runs). The low level of strictness proved to dramatically reduce (i.e., from 65 to 70%) the running time required to obtain an acceptable solution when compared to that obtained at the high level of strictness. The quality of the solutions found with a single run was considerably lower than that obtained with the any other number of runs. On the other hand, the quality of the solutions seemed to stabilize at and after 10 runs, indicating that there is no added value to the quality of the solution when 15 or 20 runs are performed. In summary, having the computational tool developed in this research execute 5 runs with the low level of strictness would generate high quality solutions in a reasonable running time. / Graduation date: 2004

The transition from second-generation (2G) to third-generation (3G) wireless cellular and cordless telephone systems requires multi-standard adaptability in a single RF receiver equipment. An important answer to this request is the use of Delta-Sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic range requirements for digital signal processing, and at the same time, add adaptability and programmability to the characteristics of a RF receiver. This thesis addresses the issues of designing a Delta-Sigma modulator for a multi-standard wireless receiver. A single-loop third-order modulator topology suitable for low power and high integration multi-standard receiver design is proposed. The trade-offs in the modulator design are also presented and explained. The modulator, which has been implemented as a part of a monolithic receiver chip, will be fabricated in a standard 0.35-��m CMOS process. The post-layout simulation results have verified the outcomes of system analysis. / Graduation date: 2004

Roy A. Paananen. / "September 22, 1952." "Based on a thesis presented for the degree of Electrical Engineer, Massachusetts Institute of Technology, 1952." / Bibliography: p. 84-85. / Army Signal Corps Contract DA36-039 sc-100, Project 8-102B-0. Dept. of the Army Project 3-99-10-022.

T.P. Cheatham. / "April 24, 1947." / Includes bibliographical references. / Army Signal Corps Contract No. W-36-039 sc-32037