Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / 1 ill. in back pocket. Vita. Abstract. Includes bibliographical references (leaves 224-228). Also available via the Internet.

Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 47-51). Also available on the World Wide Web.

Thesis (M. S. in Electrical Engineering)--Vanderbilt University, Aug. 2004. / Title from title screen. Includes bibliographical references.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The embedded system related hardware technology has experienced rapid development, and it provided the software technology with a huge space for growth. Therefore using software approaches to perform GPS receiver functions in a powerful and generic hardware platform is becoming more feasible. In this paper, the software GPS receiver technology and the design basics of the software receiver are discussed. Further in the Matlab simulation environment, the implementation of a software receiver for replacing the processing functions of ASIC in traditional GPS receivers, i.e. RF front end and multi-channel correlator, is presented. Some simulation results and implementation details are included.

The wirelessly networked opportunistic digital array radar (WNODAR) system combines opportunistic phased array and aperstructure concepts. The array elements contain standâ alone transmitâ receive (T/R) modules with no hardwire connections other than prime power and are wirelessly networked to a central controller and processor unit. A fullâ scale WNODAR operating in the VHF/UHF frequency bands (300 MHz) exhibits many favorable properties, which make the system suitable for ballistic missile defense (BMD) early warning radar (EWR) applications. In order to validate the WNODAR concepts, demonstration arrays consisting of T/R modules realized using field programmable gate array (FPGA) technology are developed. The demonstration units are frequency scaled from the projected VHF/UHF frequency range to S-band (2.4 GHz) to make use of the abundance of commercial off the shelf (COTS) wireless communication components. This research primarily relates to the development of a demonstration T/R module and the evaluation and characterization of component devices. Design, analysis and simulation of an eightâ element demonstration array using MATLAB and CST Microwave Studio were conducted to examine expected array beam patterns.

Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface.

Since its introduction in the early 1980??s, the Global Positioning System (GPS) has become an important worldwide resource. Although the primary use of GPS is for position location, the inherent timing accuracy built into the system has allowed it become an important synchronisation resource for other systems. In most cases the GPS end user only requires a position estimate without awareness of the timing and synchronisation aspects of the system. A low accuracy position (at the several-metre level) with a low update rate of about 1Hz is often acceptable. However, obtaining more accurate position estimates (at the sub-metre level) at higher update rates requires the use of differential correction signals (DGPS) and greater processing power in the receiver. Furthermore, some extra challenges arise when simultaneously gathering information from a group of independently moving remote GPS receivers (rovers) at increased sampling rates (10Hz). This creates the need for a high bandwidth telemetry system and techniques to synchronise the position measurements for tracking each rover. This thesis investigates and develops an overall solution to these problems using GPS for both position location and synchronisation. A system is designed to generate relative position information from 30 or more rovers in real-time. The important contributions of this research are as follows: a) A GPS synchronised telemetry system is developed to transport GPS data from each rover. Proof of concept experiments show why a conventional RF Local Area Network (LAN) is not suitable for this application. The new telemetry system is developed using Field Programmable Gate Array (FPGA) devices to embed both the synchronising logic and the central processor. b) A new system architecture is developed to reduce the processing load of the GPS receiver. Furthermore, the need to transfer the DGPS correction data to the rover is eliminated. Instead, the receiver raw data is processed in a centralised Kalman filter to produce multiple position estimates in real-time. c) Steps are taken to optimise the telemetry data stream by using only the bare essential data from each rover. A custom protocol is developed to deliver the GPS receiver raw data to the central point with minimal latency. The central software is designed to extract and manage common elements such as satellite ephemeris data from the central reference receiver only. d) Methods are developed to make the overall system more robust by identifying and understanding the points of failure, providing fallback options to allow recovery with minimal impact. Based on the above a system is designed and integrated using a mixture of custom hardware, custom software and off-the-shelf hardware. Overall tests show that efforts to minimise latency, minimise power requirements and improve reliability have delivered good results.

Thesis (Ph. D.)--Ohio State University, 2007. / Title from first page of PDF file. Includes bibliographical references (p. 197-204).

The United States Department of Defense has introduced two new GPS civilian signals on its “Link 2” (L2) and “Link 5” (L5) center frequencies. The first of these new civilian signals to reach full operational capability in the GPS constellation will be the L2 C signal. The L2 C signal boasts new signal structure features aimed at better tracking performance in comparison to the legacy L1 C/A signal. Amongst these are two new chip-by-chip interleaved spreading code sequences, Civilian Moderate (CM) and Civilian Long (CL), and a new, higher resolution navigation message, CNAV. The two new C codes are longer than the legacy C/A code and feature a data less pilot signal (CL) for improved tracking performance in weak signal environments. This work investigates L2 C acquisition and tracking considerations and implements algorithms for acquiring and tracking the signal in a software-defined receiver developed in MATLAB. The Emergent MATLAB L2 C (EMAL2) receiver was developed for the purpose of GPS signal simulator testing. This software-defined receiver differs from legacy receivers containing application specific integrated circuits (ASICs) in that all of EMAL2’s digital signal processing is done in software able to run on a general purpose processor. This approach offers greater flexibility and ease in configuration over ASICs for tracking a number of different types of signal structures in the receiver. The EMAL2 receiver’s design and implementation is described here-in. Initial testing of the EMAL2 receiver was conducted with live-sky signal data captured by antennas and front-ends at the University of Texas Radionavigation Laboratory (UT RNL). The data was processed by the GRID receiver (also at the UT RNL) to provide EMAL2 baseline received signal characteristics. / text

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