Fontes radioativas possuem radionuclídeos. Um radionuclídeo é um átomo com um núcleo instável, ou seja, um núcleo caracterizado pelo excesso de energia que está disponível para ser emitida. Neste processo, o radionuclídeo sofre o decaimento radioativo e emite raios gama e partículas subatômicas, constituindo-se na radiação ionizante. Então, a radioatividade é a emissão espontânea de energia a partir de átomos instáveis. A identificação correta de radionuclídeos pode ser crucial para o planejamento de medidas de proteção, especialmente em situações de emergência, definindo o tipo de fonte de radiação e seu perigo radiológico. Esta dissertação apresenta a aplicação do método de agrupamento subtrativo, implementada em hardware, para um sistema de identificação de elementos radioativos com uma resposta rápida e eficiente. Quando implementados em software, os algoritmos de agrupamento consumem muito tempo de processamento. Assim, uma implementação dedicada para hardware reconfigurável é uma boa opção em sistemas embarcados, que requerem execução em tempo real, bem como baixo consumo de energia. A arquitetura proposta para o hardware de cálculo do agrupamento subtrativo é escalável, permitindo a inclusão de mais unidades de agrupamento subtrativo para operarem em paralelo. Isso proporciona maior flexibilidade para acelerar o processo de acordo com as restrições de tempo e de área. Os resultados mostram que o centro do agrupamento pode ser identificado com uma boa eficiência. A identificação desses pontos pode classificar os elementos radioativos presentes em uma amostra. Utilizando este hardware foi possível identificar mais do que um centro de agrupamento, o que permite reconhecer mais de um radionuclídeo em fontes radioativas. Estes resultados revelam que o hardware proposto pode ser usado para desenvolver um sistema portátil para identificação radionuclídeos. / Radioactive sources include radionuclides. A radionuclide is an atom with an unstable nucleus, i.e. a nucleus characterized by excess of energy, which is available to be imparted. In this process, the radionuclide undergoes radioactive decay and emits gamma rays and subatomic particles, constituting the ionizing radiation. So, radioactivity is the spontaneous emission of energy from unstable atoms. Correct radionuclide identification can be crucial to planning protective measures, especially in emergency situations, by defining the type of radiation source and its radiological hazard. This project introduces the application of subtractive clustering method, in a hardware implemnetation, for an identification system of radioactive elements that allows a rapid and efficient identification. In software implementations, clustering algorithms, usually, are demanding in terms of processing time. Thus, a custom implementation on reconfigurable hardware is a viable choice in embedded systems, so as to achieve real-time execution as well as low power consumption. The proposed architecture for the hardware of subtractive clustering is scalable, allowing for the inclusion of more of subtractive clustering unit that operate in parallel. This provides greater flexibility to accelerate the hardware with respect to the time and area requirements. The results show that the expected cluster center can be identified with efficiently. The identification of these points can classify the radioactive elements present in a sample. Using the designed hardware, it is possible to identify more than one cluster center, which would lead to the recognition of more than one radionuclide in radioactive sources. These results reveal that the proposed hardware to subtractive cluster can be used to design a portable system for radionuclides identification.

Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.:1 Introduction 1.1 Forethoughts 1.2 Theoretical Background 1.2.1 Definitions 1.2.2 Expressing Connections between Circuit Elements 1.2.3 Global Context and Target Function 1.2.4 Problem formulation as QBF and SAT 2 Description of the Implemented Tool 2.1 Design Decisions 2.1.1 Choice of Language, Libraries and Frameworks 2.1.2 Solving the QBF Problem 2.1.3 Design of the Internally Used Meta-Model 2.1.4 User Interface Ergonomics 2.1.5 Aspects of Schematic Visualization 2.1.6 Limitations 2.2 Implemented Features 2.2.1 Basic Interaction 2.2.2 User-Defined Components 2.2.3 Generation of Circuit Symbols 2.2.4 Methods for Specifying Functional Behaviour 3 Implementation Details 3.1 Classes Involved in the Component Meta-Model 3.2 The Document Entry Class and its Factory 3.3 Model and View 3.3.1 The Model Element Hierarchy 3.3.2 The Schematics Element Hierarchy 3.4 The Quantor Interface 4 An Example Workflow 4.1 The Task 4.2 A Component Descriptor for Xilinx’ LUT6-2 4.3 Designing the Model 4.4 Computing the Desired Configuration 5 Summary and Outlook 5.1 Achieved Results 5.2 Suggested Improvements References A Acronyms and Glossary B UML Diagrams

The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is required. / Das Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt.

Embedded electronics are widely employed in cyber-physical systems (CPSes), which tightly integrate and coordinate computational and physical elements. CPSes are extensively deployed in security-critical applications and nationwide infrastructure. Perimeter security approaches to preventing malware infiltration of CPSes are challenged by the complexity of modern embedded systems incorporating numerous heterogeneous and updatable components. Global supply chains and third-party hardware components, tools, and software limit the reach of design verification techniques and introduce security concerns about deliberate Trojan inclusions. As a consequence, skilled attacks against CPSes have demonstrated that these systems can be surreptitiously compromised. Existing run-time security approaches are not adequate to counter such threats because of either the impact on performance and cost, lack of scalability and generality, trust needed in global third parties, or significant changes required to the design flow. We present a protection scheme called Run-time Enhancement of Trusted Computing (RETC) to enhance trust in CPSes containing untrusted software and hardware. RETC is complementary to design-time verification approaches and serves as a last line of defense against the rising number of inexorable threats against CPSes. We target systems built using reconfigurable hardware to meet the flexibility and high-performance requirements of modern security protections. Security policies are derived from the system physical characteristics and component operational specifications and translated into synthesizable hardware integrated into specific interfaces on a per-module or per-function basis. The policy-based approach addresses many security challenges by decoupling policies from system-specific implementations and optimizations, and minimizes changes required to the design flow. Interface guards enable in-line monitoring and enforcement of critical system computations at run-time. Trust is only required in a small set of simple, self-contained, and verifiable guard components. Hardware trust anchors simultaneously addresses the performance, flexibility, developer productivity, and security requirements of contemporary CPSes. We apply RETC to several CPSes having common security challenges including: secure reconfiguration control in reconfigurable cognitive radio platforms, tolerating hardware Trojan threats in third-party IP cores, and preserving stability in process control systems. High-level architectures demonstrated with prototypes are presented for the selected applications. Implementation results illustrate the RETC efficiency in terms of the performance and overheads of the hardware trust anchors. Testbenches associated with the addressed threat models are generated and experimentally validated on reconfigurable platform to establish the protection scheme efficacy in thwarting the selected threats. This new approach significantly enhances trust in CPSes containing untrusted components without sacrificing cost and performance. / Ph. D.

A Cyber-Physical System (CPS) is a large-scale, distributed, embedded system, consisting of various components that are glued together to realize control, computation and communication functions. Although these systems are complex, they are ubiquitous in the Internet of Things (IoT) era of autonomous vehicles/drones, smart homes, smart grids, etc. where everything is connected. These systems are vulnerable to unauthorized penetration due to the absence of proper security features and safeguards to protect important information. Examples such as the typewriter hack involving subversive chips resulting in leakage of keystroke data and hardware backdoors crippling anti-aircraft guns during an attack demonstrate the need to protect all system functions. With more focus on securing a system, trust in untrusted components at the integration stage is of a higher priority. This work builds on a red-black security system, where an architecture testbed is developed with critical and non-critical IP cores and subjected to a variety of Hardware Trojan Threats (HTTs). These attacks defeat the classic trusted hardware model assumptions and demonstrate the ability of Trojans to evade detection methods based on physical characteristics. A novel metric is defined for hardware Trojan detection, termed as HTT Detectability Metric (HDM) that leverages a weighted combination of normalized physical parameters. Security analysis results show that using HDM, 86% of the implemented Trojans were detected as compared to using power consumption, timing variation and resource utilization alone. This led to the formulation of the security requirements for the development of a novel, distributed and secure methodology for enhancing trust in systems developed under untrusted environments called FIDelity Enhancing Security (FIDES). FIDES employs a decentralized information flow control (DIFC) model that enables safe and distributed information flows between various elements of the system such as IP cores, physical memory and registers. The DIFC approach annotates/tags each data item with its sensitivity level and the identity of the participating entities during the communication. Trust enhanced FIDES (TE-FIDES) is proposed to address the vulnerabilities arising from the declassification process during communication between third-party soft IP cores. TE-FIDES employs a secure enclave approach for preserving the confidentiality of the sensitive information in the system. TE-FIDES is evaluated by targeting an IoT-based smart grid CPS application, where malicious third-party soft IP cores are prevented from causing a system blackout. The resulting hardware implementation using TE-FIDES is found to be resilient to multiple hardware Trojan attacks. / Ph. D.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

A ferramenta ChipCflow vem sendo desenvolvida nos últimos quatro anos, inicialmente a partir de um projeto de arquitetura a fluxo de dados dinâmico em hardware reconfigurável, mas agora como uma ferramenta de compilação. Ela tem como objetivo a execução de algoritmos por meio do modelo de arquitetura a fluxo de dados associado ao conceito de dispositivos parcialmente reconfiguráveis. Sua característica principal é acelerar o tempo de execução de programas escritos em Linguagem de Programação de Alto Nível (LPAN), do inglês, High Level Languages, em particular nas partes mais intensas de processamento. Isso é feito por meio da implementação dessas partes de código diretamente em hardware reconfigurável - utilizando a tecnologia Field-programmable Gate Array (FPGA) - aproveitando ao máximo o paralelismo considerado natural do modelo a fluxo de dados e as características do hardware parcialmente reconfigurável. Neste trabalho, o objetivo é a prova de conceito do processo de partição e do protocolo de comunicação entre as partições definidas a partir de um Grafo de Fluxo de Dados (GFD), para a execução direta em hardware reconfigurável utilizando Reconfiguração Parcial Dinâmica (RPD). Foi necessário elaborar um mecanismo de partição e protocolo de comunicação entre essas partições, uma vez que a RPD insere características tecnológicas limitantes não encontradas em hardwares reconfiguráveis mais tradicionais. O mecanismo criado se mostrou parcialmente adequado à prova de conceito, significando a possibilidade de se executar GFDs na plataforma parcialmente reconfigurável. Todavia, os tempos de reconfiguração inviabilizaram a proposta inicial de se utilizar RPD para diminuir o tempo de tag matching dos GFDs dinâmicos / The ChipCflow tool has been developed over the last four years, initially from an architectural design the flow of Dynamic Data in reconfigurable hardware, but now as a compilation tool. It aims to run algorithms using the model of the data flow architecture associated with the concept of partially reconfigurable devices. Its main feature is to accelerate the execution time of programs written in High Level Languages, particularly in the most intense processing. This is done by implementing those parts of code directly in reconfigurable hardware - using FPGA technology - leveraging the natural parallelism of the data flow model and characteristics of the partially reconfigurable hardware. In this work, the main goal is the proof of concept of the partition process and protocol communication between the partitions defined from Data Flow Graph for direct execution in reconfigurable hardware using Active Partial Reconfiguration. This required a mechanism to partition and a protocol for communication between these partitions, since the Active Partial Reconfiguration inserts technological features limiting not found in traditional reconfigurable hardware. The mechanism developed is show to be partially adequate to the proof of concept, meaning the ability to run Data Flow Graphs in a platform that is partially reconfigurable. However, the reconfiguration time inserts a great overhead into the execution time, which made the proposal of the use of Active Partial Reconfiguration to decrease the time matching Data Flow Graph unfeasible

O número de acidentes veiculares têm aumentado mundialmente e a principal causa associada a estes acidentes é a falha humana. O desenvolvimento de veículos autônomos é uma área que ganhou destaque em vários grupos de pesquisa do mundo, e um dos principais objetivos é proporcionar um meio de evitar estes acidentes. Os sistemas de navegação utilizados nestes veículos precisam ser extremamente confiáveis e robustos o que exige o desenvolvimento de soluções específicas para solucionar o problema. Devido ao baixo custo e a riqueza de informações, um dos sensores mais utilizados para executar navegação autônoma (e nos sistemas de auxílio ao motorista) são as câmeras. Informações sobre o ambiente são extraídas por meio do processamento das imagens obtidas pela câmera, e em seguida são utilizadas pelo sistema de navegação. O objetivo principal desta tese consiste do projeto, implementação, teste e otimização de um comitê de Redes Neurais Artificiais utilizadas em Sistemas de Visão Computacional para Veículos Autônomos (considerando em específico o modelo proposto e desenvolvido no Laboratório de Robótica Móvel (LRM)), em hardware, buscando acelerar seu tempo de execução, para utilização como classificadores de imagens nos veículos autônomos desenvolvidos pelo grupo de pesquisa do LRM. Dentre as contribuições deste trabalho, as principais são: um hardware configurado em um FPGA que executa a propagação do sinal em um comitê de redes neurais artificiais de forma rápida com baixo consumo de energia, comparado a um computador de propósito geral; resultados práticos avaliando precisão, consumo de hardware e temporização da estrutura para a classe de aplicações em questão que utiliza a representação de ponto-fixo; um gerador automático de look-up tables utilizadas para substituir o cálculo exato de funções de ativação em redes MLP; um co-projeto de hardware/software que obteve resultados relevantes para implementação do algoritmo de treinamento Backpropagation e, considerando todos os resultados, uma estrutura que permite uma grande diversidade de trabalhos futuros de hardware para robótica por implementar um sistema de processamento de imagens em hardware. / The number of vehicular accidents have increased worldwide and the leading associated cause is the human failure. Autonomous vehicles design is gathering attention throughout the world in industry and universities. Several research groups in the world are designing autonomous vehicles or driving assistance systems with the main goal of providing means to avoid these accidents. Autonomous vehicles navigation systems need to be reliable with real-time performance which requires the design of specific solutions to solve the problem. Due to the low cost and high amount of collected information, one of the most used sensors to perform autonomous navigation (and driving assistance systems) are the cameras.Information from the environment is extracted through obtained images and then used by navigation systems. The main goal of this thesis is the design, implementation, testing and optimization of an Artificial Neural Network ensemble used in an autonomous vehicle navigation system (considering the navigation system proposed and designed in Mobile Robotics Lab (LRM)) in hardware, in order to increase its capabilites, to be used as image classifiers for robot visual navigation. The main contributions of this work are: a reconfigurable hardware that performs a fast signal propagation in a neural network ensemble consuming less energy when compared to a general purpose computer, due to the nature of the hardware device; practical results on the tradeoff between precision, hardware consumption and timing for the class of applications in question using the fixed-point representation; a automatic generator of look-up tables widely used in hardware neural networks to replace the exact calculation of activation functions; a hardware/software co-design that achieve significant results for backpropagation training algorithm implementation, and considering all presented results, a structure which allows a considerable number of future works on hardware image processing for robotics applications by implementing a functional image processing hardware system.

Com a tecnologia digital, as redes de comunicação têm sido de fundamental importância para o bom funcionamento das subestações de energia elétrica. Criado em 2002, o padrão IEC 61850 busca harmonizar a diversidade de equipamentos e fabricantes, e possibilitar a integração de dados para que o máximo de benefícios possa ser extraído. Nesse contexto, o protocolo GOOSE (Generic Object Oriented Substation Event), pertinente ao padrão IEC 61850, é um datagrama multicast concebido para funcionar na rede local ou de longa distância que interliga as subestações de energia elétrica. Nos ambientes de longa distância, o tráfego de dentro para fora, e vice-versa, deveria passar por um firewall. Porém, a tecnologia de firewall atual não é capaz de inspecionar as mensagens GOOSE reais ou originadas a partir de um ataque, e afeta o tempo de transferência das mesmas, que, no enlace de comunicação, não deve exceder 5ms. Dessa forma, o objetivo deste trabalho é desenvolver um firewall em hardware reconfigurável, por meio da plataforma NetFPGA, de modo que o incremento no tempo de propagação de uma mensagem GOOSE, Tipo 1A (Trip), ao transpor o dispositivo de segurança, não ultrapasse 20% do tempo total destinado ao enlace de comunicação. Por ter a capacidade de ser um acelerador, construído por meio de hardware reconfigurável FPGA (Field Programmable Gate Array), a NetFPGA conduz enlaces Gigabit, e torna possível examinar e estabelecer regras iniciais de autorização ou negação para o tráfego de mensagens GOOSE, manipulando os campos do quadro ISO/IEC 8802-3. O incremento no tempo máximo de propagação de uma mensagem com 1518 bytes foi de 77,39 μs, com 77,38 μs de tempo médio. Um algoritmo de criptografia e outro de autenticação também foram testados e mensagens falsas não conseguiram transpor o firewall. No momento atual da pesquisa, concluiu-se que o firewall em NetFPGA, pertinente ao conjunto de recursos de hardware e software destinados a garantir a segurança de uma rede, é capaz de rejeitar mensagens GOOSE falsas e fornecer segurança aos dispositivos ativos de uma subestação, sem atrasos adicionais superiores a 1ms. / With the digital technology, the communication networks have been of fundamental importance for the good performance of power substations. Created in 2002, the IEC 61850 standard seeks for harmonization of the different equipment and manufacturers, enabling the integration of data for maximum performance. In this context, the GOOSE (Generic Object Oriented Substation Event) message, concerning the IEC 61850 standard, is a multicast datagram, designed to operate in LAN or WAN that connects power substations. In the long-distance environment, the propagation time in the communication link must not exceed 5ms. The current firewall technology is not able to differ true GOOSE messages from the ones originated from an attack, and it affects the transfer time of messages. The objective of this research is to develop a reconfigurable firewall hardware, using the NetFPGA platform, so that the increase in propagation time of a GOOSE message, Type 1A (Trip), does not exceed 20% of the total time allocated to the link communication. Due to the ability of NetFPGA of being an accelerator, and having been built by using reconfigurable FPGA (Field Programmable Gate Array) leading to Gigabit links, it was possible to examine and establish initial rules of authorization or denial of GOOSE messages by manipulating some of the fields from the table ISO/IEC 8802-3. The increase in the maximum propagation time of a message of 1518 bytes was 77.39 μs, with the average of 77.38 μs. Fake messages failed to cross the firewall. Results from a process of authentication and encryption were also presented. At the present study, it has been concluded that the firewall using NetFPGA, concerning the hardware and software in order to ensure the security of a network, is able to reject false GOOSE messages and provide security to devices of a power substation without time increments greater than 1ms.

Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2017-10-25T13:48:51Z No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5) / Made available in DSpace on 2017-10-25T13:48:52Z (GMT). No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5) Previous issue date: 2017-09-21 / PADIS - Programa de apoio ao desenvolvimento tecnológico da indústria de semicondutores / O presente trabalho consiste em uma proposta de uma plataforma reconfigurável para testes de módulos de memória SDRAM DDR3. Testadores de módulos de memória consistem em sistemas de arquiteturas fechadas, nos quais o usuário possui pouca flexibilidade em sua utilização, transporte e são na maioria das vezes sistemas volumosos próprios para uso em bancadas. Neste cenário, uma plataforma portátil de baixo custo, que possibilite ao usuário descrever os algoritmos de teste torna-se interessante. A plataforma desenvolvida utiliza de Field Programmable Gate Arrays (FPGA) o que proporciona a característica de reconfiguração. Neste projeto foi proposta e validada uma estratégia de injeção de falhas do tipo Stuck-At-Zero, aliado a um sistema automático para coleta de vetores de teste e para a síntese em diferentes frequências de acesso aos módulos de memória. A etapa de validação do protótipo desenvolvido possibilitou reportar a captura de 131.751 falhas, graças ao framework criado para acompanhar a tarefa de injeção de falhas. / This work consists on a proposal of a DDR3 SDRAM memory module reconfigurable test platform. Memory module testers are usually closed architecture systems, in which the user has little flexibility in their use. In this scenario, a low-cost portable platform, which enables the user to describe his own test algorithm becomes interesting. This work explores the use of Field Programmable Gate Arrays (FPGAs) in order to construct a fully reconfigurable testing platform. In this work a Stuck-At-Zero fault injection strategy was proposed and validated. Results report the success in executing fault detection algorithms as well as the software framework developed for the fault injection campaign.