Dans le cadre de l’avion plus électrique, les avionneurs cherchent à remplacer les commandes de vol hydrauliques par des commandes de vol électriques, avec pour intérêt de diminuer le poids, et d’améliorer la flexibilité des équipements aéronautiques. Sachant que sur un A380, la distance cumulée pour les câbles peut atteindre plus de 500 km, la solution consistant à faire cohabiter les transmissions de données et de puissances au sein de mêmes câbles grâce à la technologie CPL pourrait contribuer à réduire la masse de câble dans un avion. Cependant les câbles de puissance n’ont pas été dimensionnés pour transmettre un signal informationnel, et les équipements présents sur le réseau sont source de bruits. Dans ce contexte nous souhaitons montrer la faisabilité d’une transmission CPL soumise aux contraintes avioniques tout en respectant les normes aéronautiques. La première partie des travaux a consisté à mesurer le canal de propagation sur un banc de test représentatif d’un environnement aéronautique. Le canal de propagation est composé de deux coupleurs de type inductif ou capacitif dont le but est de connecter les câbles de télécommunication au réseau de puissance et d’une paire bifilaire torsadée de puissance d’une longueur de 32 m représentative d’un réseau HVDC ±270 V. Nous avons alors testé trois architectures différentes : l’architecture point-À-Point avec coupleur capacitif, l’architecture point-À-Point avec coupleur inductif et l’architecture point-À-Multipoints avec coupleur inductif. Le but de ces mesures a été d’évaluer la fonction de transfert du canal sur la bande [1 ; 100] MHz. Nous avons alors calculé les éléments caractéristiques du canal comme la bande de cohérence et l’étalement des retards. Après la caractérisation du canal de propagation, nous avons choisi et dimensionné les algorithmes de traitement du signal au regard des spécifications aéronautiques à savoir : un débit utile de 10 Mbit/s, un temps de latence de 167-334 μs, un TEB de 10-12 et le respect du gabarit de la DO-160 en émission conduite. Au regard de la fonction de transfert du canal, nous avons choisi d’utiliser l’OFDM comme technique de transmission. Ainsi, à l’aide de la caractérisation du canal de propagation nous avons au cours d’une étude paramétrique défini les paramètres de la transmission OFDM au regard des spécifications de débit et de temps réel. Dans un second temps, nous avons implanté les paramètres OFDM ainsi que la modélisation du canal de propagation dans une chaine de transmission Matlab. Cette chaine nous a alors permis de vérifier les paramètres issues de l’étude paramétrique ainsi que de définir le système de codage de canal (Reed-Solomon et code convolutif) pour respecter les spécifications aéronautiques. La dernière partie de cette thèse a consisté en l’étude du système de synchronisation. Du fait de la stabilité du canal de propagation, nous avons considéré une synchronisation fine du système lors d’une phase d’initialisation puis nous nous somme focalisé sur le dimensionnement d’un système de suivi dans le but de corriger le décalage de fenêtre FFT dû au défaut de fréquence d’échantillonnage. Pour limiter les pertes de débit lors de la phase de suivi, nous avons proposé une estimation de l’erreur de fréquence d’échantillonnage sur la phase des données reçues sur une période de 20 symboles OFDM. / In the new aircrafts, hydraulic flight control systems are replaced by electric flight control systems. The main interests are a better flexibility of the aeronautical equipments and a decrease in maintenance costs and construction costs, but the major problem is the increasing of the wires length. In order to decrease this length, it has been proposed to use power line communications (PLC) technology for flight control systems. The decrease of wire will first decrease aircraft weight and therefore the consumption of kerosene and on the other hand will simplify maintenance and construction. The first part of this work is the measurement and the characterisation of the propagation channel on an aeronautic test bench (with HVDC supply and loads). This channel is composed of two couplers (inductive or capacitive) in order to connect the telecommunication system on the power wires with galvanic isolation and one twisted pair of 32 m longs. We have tested three architectures: the point-To-Point architecture with capacitive coupler, the point-To-Point architecture with inductive coupler and the point-To-Multipoint architecture with inductive coupler. The purpose of these measurements is to measured the transfer function on the [1 ; 100] MHz bandwidth. Then, we have computed the channel parameters like the coherence bandwidth and the delay spread. The second step was the design of the signal processing algorithm in order to satisfy the aeronautical specifications: a useful bite rate of 10 Mbit/s, a latency of 167- 334 μs, a BER of 10-12 and the respect of the DO-160 gauge in conducted emissions. For the transmissions, we have chosen the OFDM technology which has been use with success in other PLC systems. With the channel characterization, we have proposed a parametric study in order to define the OFDM parameters to satisfy the bite rate and the real time constraints. After, we compute digital simulations with Matlab to check the OFDM parameters. With these simulations, we have also defined the channel coding parameters (Reed-Solomon and convolutional coding) to satisfy the aeronautical specifications. The last part of this study was the design of the synchronisation system. Because of the channel stability, we considered a precise synchronisation after an initialisation period. Then, we focus on the estimation of the FFT shift, due to the sampling frequency shift, during a following-Up period. In order to avoid the decrease of the latency and the bitrate due to the pilot symbols or pilot sub-Carriers insertion, we proposed to correct the FFT shift with the receive data thanks to the maximal likelihood algorithm.

In the wireless sensor network, the WLAN interference, multi-path fading andattenuation are the main reason for packets’ corruption. Forward errorcorrection is one of the methods for error mitigation. Many coding methods aredesigned to improve the reliability of wireless channel. However, none of thesecoding methods could handle the burst errors that widely exist in wirelesschannel and are mainly responsible for packet corruption. Interleaving isintroduced to robust these coding methods and make those corrupted packetsavailable to be corrected by spreading the burst errors. The Reed-Solomon(15,7) block code is used as the forwarding error correction in theseexperiments. In this paper, seven different symbol interleaving will be firstlysimulated in the Matlab platform under four different channels to evaluate theirpacket error rate performances. Then, two of the seven interleaving with betterperformance and the simplest interleaving algorithm, general block interleavingwill be implemented in the TinyOS platform, and they will be compared witheach other from packet error rate, interleaving time and memory consumptionaspects. Experiments show that, for theoretical channel, interleaving plays animportant role to enhance the capability to correct the corrupted packets exceptfor Rayleigh channel, in which the impact of interleaving is generally slight.Meanwhile for the channel under IEEE 802.11b/g interference, interleavingenhance more than 10% PER in the receiver. However for MFA channel, theenhancement is slight, only 1.85%. Convolutional interleaving has the best PERperformance in AWGN channel and the channel with deterministic SER, whilematrix interleaving has the lowest PER in WLAN affected channel. In thelatency and memory consumption aspect, For the same packet length, generalblock interleaving has the shortest interleaving time while matrix interleavinghas the longest. In the same interleaving algorithm, the execution time becomeslonger with growth of packet size. Within the same interleaving method, thelonger the packet size is, the more memory that would be consumed. Under thesame interleaving length, general block interleaving consumes least memoryand convolutional interleaving has the largest memory consumption.

In this paper the performance of executing Cauchy Reed-Solomon (CRS) coding on the GPU is evaluated and compared with execution on the CPU. Three different prototypes are developed. One is sequential and developed in C++, the other two are developed utilizing C++ and OpenCL. The measurements are done by comparing the execution time of different data block sizes ranging from 16KB up to 256MB with two different encoding ratios, 9/12 and 10/16. The measurements are done on an Intel CPU with 4 cores with an integrated graphics card and an AMD graphics card. The OpenCL prototypes are executed with three different targets, the CPU, the integrated graphics card and the AMD graphics card. The sequential prototype is executed on the same CPU, but on a single core. The results from the measurements show that the GPU is faster than the CPU on larger data sizes. The highest measured throughput is achieved with the multithreaded CPU prototypes (OpenCL executed on the CPU) for sizes around 1MB. / I den här rapporten genomförs prestandatester för exekvering av Cauchy Reed-Solomon (CRS) coding på grafikkortet och jämförs med exekvering på en CPU. Tre olika prototyper har utvecklats. En är sekventiell och utvecklad i C++, de två andra är utvecklade i OpenCL och C++. Testerna genomförs genom tidtagning på olika stora datablock, från 16KB upp till 256MB med olika enkodnings ratios, 9/12 och 10/16. CPU:n som används i testerna är en Intel CPU med 4 kärnor, och grafikkorten som används är det integrerade grafikkortet på CPU:n samt ett grafikkort från AMD. OpenCL prototyperna exekveras med tre olika inställningar, CPU för multitrådat, det integrerade Intel grafikkortet och det dedikerade AMD grafikkortet. Den sekventiella prototypen exekveras på samma CPU, men med en kärna. Resultaten från experimenten visar att grafikkorten är snabbare än CPU:n för större datablock. Den prototyp som fick högst genomströmning av data var den multitrådade CPU prototypen för datablock i storleksordningen 1MB.

Tato diplomová práce pojednává o zmírnění bitové chybovosti bezkabelového optického spoje s užitím principu reciprocity aplikovaného na komunikační kanál, spolu s možností kódování přenášených dat. V této práci je implementováno LDPC a Reed-Solomonovo kódování pro jejich vyhovující vlastnosti. Zbytková rámcová chybovost je vypočtena a k dispozici jako výstup systému, který je implementovaný v hradlovém poli (FPGA).

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquema / García Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753 / TESIS / Premios Extraordinarios de tesis doctorales

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In this paper, we develop a scheme to recover a single erasure when using a Cartesian code,in the context of a distributed storage system. Particularly, we develop a scheme withconsiderations to minimize the associated bandwidth and maximize the associateddimension. The problem of recovering a missing node's data exactly in a distributedstorage system is known as theexact repair problem. Previous research has studied theexact repair problem for Reed-Solomon codes. We focus on Cartesian codes, and show wecan enact the recovery using a linear exact repair scheme framework, similar to the oneoutlined by Guruswami and Wooters in 2017. / Master of Science / Distributed storage systems are systems which store a single data file over multiple storage nodes. Each storage node has a certain storage efficiency, the "space" required to store the information on that node. The value of these systems, is their ability to safely store data for extended periods of time. We want to design distributed storage systems such that if one storage node fails, we can recover it from the data in the remaining nodes. Recovering a node from the data stored in the other nodes requires the nodes to communicate data with each other. Ideally, these systems are designed to minimize the bandwidth, the inter-nodal communication required to recover a lost node, as well as maximize the storage efficiency of each node. A great mathematical framework to build these distributed storage systems on is erasure codes. In this paper, we will specifically develop distributed storage systems that use Cartesian codes. We will show that in the right setting, these systems can have a very similar bandwidth to systems build from Reed-Solomon codes, without much loss in storage efficiency.

Detta arbete är ett examensarbete i matematik på kandidatnivå vid Växjö universitet. Det är en studie av kodningsteori i allmänhet med fokusering på cykliska koder och Reed-Solomon-koder i synnerhet. Reed-Solomon-koderna används för att skapa McElieces kryptosystem. En kortfattad analys av McElieces kryptosystems säkerhet görs tillsammans med en genomgång av kända sätt att forcera denna typ av kryptosystem. Här visar det sig att användning av Reed-Solomon-kod försvagar kryptosystemet i förhållande till om den ursprungligt föreslagna Goppa-koden används. För att kunna göra denna säkerhetsanalys görs också en kortfattad genomgång av komplexitetsteori och vad det innebär att ett problem är NP-fullständigt. Nyckelord: Kodningsteori, Kodteori, Cykliska koder, BCH-koder, Reed-Solomon-koder, McElieces kryptosystem, Kryptering, Kodforcering, Komplexitetsteori, NP-fullständigt / This work is produced on bachelor level in mathematics at University of Växjö. It is a study of coding theory with focus on cyclic codes in general and Reed-Solomon codes in detail. Reed-Solomon codes are used for implementing McEliece's crypto system. A short analysis of McEliece's crypto system security is also made together with a description of some known ways to break this type of cryptosystem. It is shown that using Reed-Solomon codes weaken this cryptosystem compared to using the original supposed Goppa codes. The security analyse also need a short summary of complexity theory and what it means that a problem is NP-complete. Keywords: Coding theory, Cyclic codes, BCH codes, Reed-Solomon codes, McEliece's cryptography system, Cryptography, Code breaking, Complexity theory, NP-complete