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Artificial neural networks (ANN) have found extensive use in solving real-world problems in recent years, where their exceptional information processing is the main advantage. Facing increasingly complex problems, there is a need to improve their information processing. In this thesis, we explore new ways of synthesizing ANNs by reducing the synthesis problem to the Boolean satisfiability problem (SAT) that is, the problem of determining whether a given Boolean formula is satisfiable. Also known as the SAT problem, it aims to determine if there exists such a combination of Boolean variables in a propositional formula for which the formula evaluates to true. We derived a general formula in conjunctive normal form (CNF) representing the synthesis of a neural network. Given randomly generated datasets, we were able to construct CNF formulas whose satisfying assignments encode neural networks consistent with the datasets. These formulas were run through an off-the-shelf SAT solver, where the outputted models simulated the synthesis of neural networks consistent with the datasets. The experiments conducted in this thesis showed that our method had the ability to produce feed-forward neural networks of varying sizes consistent with randomly generated datasets of binary strings.

Automated trust negotiation is the process of establishing trust between entities with no prior relationship through the iterative disclosure of digital credentials. One approach to negotiating trust is for the participants to exchange access control policies to inform each other of the requirements for establishing trust. When a policy is received at runtime, a compliance checker determines which credentials satisfy the policy so they can be disclosed. In situations where several sets of credentials satisfy a policy and some of the credentials are sensitive, a compliance checker that generates all the sets is necessary to insure that the negotiation succeeds whenever possible. Compliance checkers designed for trust management do not usually generate all the satisfying sets. In this thesis, we present two practical algorithms for generating all satisfying sets given a compliance checker that generates only one set. The ability to generate all of the combinations provides greater flexibility in how the system or user establishes trust. For example, the least sensitive credential combination could be disclosed first. These ideas have been implemented in TrustBuilder, our prototype system for trust negotiation.

Expressiveness, and more recently, succinctness, are two central concerns of finite model theory and descriptive complexity theory. Succinctness is particularly interesting because it is closely related to the complexity-theoretic trade-off between parallel time and the amount of hardware. We develop new bounds on the expressiveness and succinctness of first-order logic with two variables on finite words, present a related result about the complexity of the satisfiability problem for this logic, and explore a new approach to the generalized star-height problem from the perspective of logical expressiveness. We give a complete characterization of the expressive power of first-order logic with two variables on finite words. Our main tool for this investigation is the classical Ehrenfeucht-Fra¨ıss´e game. Using our new characterization, we prove that the quantifier alternation hierarchy for this logic is strict, settling the main remaining open question about the expressiveness of this logic. A second important question about first-order logic with two variables on finite words is about the complexity of the satisfiability problem for this logic. Previously it was only known that this problem is NP-hard and in NEXP. We prove a polynomialsize small-model property for this logic, leading to an NP algorithm and thus proving that the satisfiability problem for this logic is NP-complete. Finally, we investigate one of the most baffling open problems in formal language theory: the generalized star-height problem. As of today, we do not even know whether there exists a regular language that has generalized star-height larger than 1. This problem can be phrased as an expressiveness question for first-order logic with a restricted transitive closure operator, and thus allows us to use established tools from finite model theory to attack the generalized star-height problem. Besides our contribution to formalize this problem in a purely logical form, we have developed several example languages as candidates for languages of generalized star-height at least 2. While some of them still stand as promising candidates, for others we present new results that prove that they only have generalized star-height 1.

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Because of the importance of undecidability and the concern with the high complexity of automated reasoning, a few interval-based temporal description logics (ITDLs) have been designed. Moreover, most existing ITDLs are not able to specify the lengths of intervals. In other words, they are not metric. On the other hand, some domains (e.g., medicine) are inherently interval-based, and require a metric logic in order to formalize defined processes and to check process consistency. Hence, a metric interval-based temporal description logic is required. In this thesis, we introduce such a logic (MITDL) along with two algorithms for the satisfiability checking of its formulas. We first introduce an interval-based temporal logic, called IMPNL, inspired by Metric Propositional Neighbourhood Logic. We also present a sound, com- plete and terminating tableau-based algorithm for checking the satisfiability of IMPNL formulas. Afterwards, we combine a restricted version of IMPNL (IMPNL without a negation operator) with the ALC description logic to form a MITDL. We propose two tableau-based algorithms for checking the satisfia- bility of MITDL formulas. We show and prove they are sound, complete and terminate. These algorithms have PSpace and 2NExp-Time complexities. As a proof of concept, we use IMPNL and MITDL to model some clinical practice guidelines (CPG) and check their consistency. We compare MITDL with several languages commonly used for modeling CPGs. / Thesis / Doctor of Science (PhD)

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Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and Verilog. The modeling at the behavioral level not only allows for better representation and understanding of the design, but also allows for encapsulation of the sub-modules as well, thus increasing productivity. Despite these benefits, validating a RTL design is not necessarily easier. Today, design validation is considered one of the most time and resource consuming aspects of hardware design. The high costs associated with late detection of bugs can be enormous. Together with stringent time to market factors, the need to guarantee the correct functionality of the design is more critical than ever. The work done in this thesis tackles the problem of RTL design validation and presents new frameworks for functional test generation. We use branch coverage as our metric to evaluate the quality of the generated test stimuli. The initial effort for test generation utilized simulation based techniques because of their scalability with design size and ease of use. However, simulation based methods work on input spaces rather than the DUT's state space and often fail to traverse very narrow search paths in large input spaces. To encounter this problem and enhance the ability of test generation framework, in the following work in this thesis, certain design semantics are statically extracted and recurrence relationships between different variables are mined. Information such as relations among variables and loops can be extremely valuable from test generation point of view. The simulation based method is hybridized with Z3 based symbolic backward execution engine with feedback among different stages. The hybridized method performs loop abstraction and is able to traverse narrow design paths without performing costly circuit analysis or explicit loop unrolling. Also structural and functional unreachable branches are identified during the process of test generation. Experimental results show that the proposed techniques are able to achieve high branch coverage on several ITC'99 benchmark circuits and their modified variants, with significant speed up and reduction in the sequence length. / Master of Science