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In general, to compute the modular inverse is very important in information security, many encrypt/decrypt and signature algorithms always need to use it. In 2007, Liu, Horng, and Liu proposed a variation on Euclidean algorithm, which can calculate the modular inverses as simple as calculate GCDs. This paper analyzes another type of left-shift binary GCD algorithm, which is suitable for the variation and that needs the fewer bit-operations than LSBGCD, which is analyzed by Shallit, and Sorenson.

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abstract: Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed. Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced. Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method. Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed. Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing. A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.

Thesis--Auburn University, 2010. / Abstract. Includes bibliographic references (p.162-167).

Analog and mixed signal device testing is resource intensive due to the spectral and temporal speci cations of the input/output interface signals. These devices and circuits are commonly validated by parametric speci fication tests to ensure compliance with the required performance criteria. Analog signal complexity increases resource requirements for the Automatic Test Equipment (ATE) systems used for commercial testing, making mixed signal testing resource ine cient as compared to digital structural testing. This dissertation proposes and implements a test ecosystem to address these constraints where Built In Self Test (BIST) modules are designed for internal stimulus generation. Data learning and processing algorithms are developed for output response shaping. This modi ed output response is then compared against the established performance matrices to maintain test quality with low cost receiver hardware. BIST modules reduce dependence on ATE resources for stimulus and output observation while improving capability to test multiple devices in parallel. Data analysis algorithms are used to predict specification parameters based on learning methods applied to measurable device parameters. Active hardware resources can be used in conjunction with post processing resources to implement complex speci cation based tests within the hardware limitations. This dissertation reviews the results obtained with the consolidated approach of using BIST, output response analysis and active hardware resources to reduce test cost while maintaining test quality. / text

Transistor scaling has kept up with Moore's law with a doubling of the number of transistors on a chip. More logic on a chip means more opportunities for manufacturing defects to slip in. This, in turn, has made processor testing after manufacturing a significant challenge. At-speed functional testing, being completely non-intrusive, has been seen as the ideal way of testing chips. However for processor testing, generating instruction level tests for covering all faults is a challenge given the issue of scalability. Data-path faults are relatively easier to control and observe compared to control-path faults. In this research we present a novel method to generate instruction level tests for hard to detect control-path faults in a processor. We initially map the gate level stuck-at fault to the Register Transfer Level (RTL) and build an equivalent faulty RTL model. The fault activation and propagation constraints are captured using Control and Data Flow Graphs of the RTL as a Liner Temporal Logic (LTL) property. This LTL property is then negated and given to a Bounded Model Checker based on a Bit-Vector Satisfiability Module Theories (SMT) solver. From the counter-example to the property we can extract a sequence of instructions that activates the gate level fault and propagates the fault effect to one of the observable points in the design. Other than the user supplying instruction constraints, this approach is completely automatic and does not require any manual intervention. Not all the design behaviors are required to generate a test for a fault. We use this insight to scale our previous methodology further. Underapproximations are design abstractions that only capture a subset of the original design behaviors. The use of RTL for test generation affords us two types of under-approximations: bit-width reduction and operator approximation. These are abstractions that perform reductions based on semantics of the RTL design. We also explore structural reductions of the RTL, called path based search, where we search through error propagation paths incrementally. This approach increases the size of the test generation problem step by step. In this way the SMT solver searches through the state space piecewise rather than doing the entire search at once. Experimental results show that our methods are robust and scalable for generating functional tests for hard to detect faults. / text

Zugl.: Dresden, Techn. Univ., Diss., 2005