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When implementing syncronous filters with global clock nets, a substantial amount of energy is consumed in the clock net. Hence, it is interesting to reduce the size of the clock net, which in turn will reduce the total energy consumption. One way to acheive this, is to create a SIC (Structured Interfacing of Computational elements) since such a structure can be created without a global clock net. Our results show that a fifth order wavedigital filter with a sample rate of at least 10M samples/sec may be achieved

This research has discussed the graphene growth mechanism and the achievement, the main purpose is to try the best method to grow graphene which is large size, uniform, and continue. The main issue is about growth and characterizations in full text which is separated by thermal annealing 6-H SiC(001) and chemical vapor deposition on the copper foil to grow graphenen. For instances, to adjust the growth parameters and the growth methods to get graphene and to control the quality, to analysis the number of layers, to research the characterizations during growth process, and to find the better transfer method are all the important focus in this paper. The morphology of samples is studied by SEM, AFM, STM, OM and so on, further the thickness of graphene layers can be observed by AFM and STM. Due to the limit of instruments, the thickness of graphene layer (~0.35 nm) and the thickness of 6-H SiC(001) steps (~1.5 nm) are not easy to observe actually. Raman spectroscopy is the main analysis tool I have employed, it is the fast way to calculate the number of layers (G, 2D band). In addition, Raman scattering is able to know the information of electronic structure variation (2D band), to investigate the stress which is caused by substrate and to estimate the quality of graphene (D, G band). Finally, I take chemical vapor deposition to grow graphenen on the copper foil. Sample is successfully transferred onto SiO2, and the number of graphene layers is estimated to be about two and the structure is AA stacking from these data. The data also shows the graphene is large size, uniform, and continue.

<p>The importance of simulation is increasing in the researchon semiconductor devices and materials. Simulations are used toexplore the characteristics of novel devices as well asproperties of the semiconductor materials that are underinvestigation, i.e. generally materials where the knowledge isinsufficient. A wide range of simulation methods exists, andthe method used in each case is selected according to therequirements of the work performed. For simulations of newsemiconductor materials, extremely small devices, or deviceswhere non-equilibrium transport is important, the Monte Carlo(MC) method is advantageous, since it can directly exploit themodels of the important physical processes in the device.</p><p>One of the semiconductors that have attracted a lot ofattraction during the last decade is silicon carbide (SiC),which exists in a large number of polytypes, among which3C-SiC, 4H-SiC and 6H-SiC are most important. Although SiC hasbeen known for a very long time, it may be considered as a newmaterial due to the relatively small knowledge of the materialproperties. This dissertation is based on a number of MCstudies of both the intrinsic properties of different SiCpolytypes and the qualities of devices fabricated by thesepolytypes. In order to perform these studies a new full-bandensemble device MC simulator, the General Monte CarloSemiconductor (GEMS) simulator was developed. Algorithmsimplemented in the GEMS simulator, necessary when allmaterial-dependent data are numerical, and for the efficientsimulation of a large number of charge carriers in high-dopedareas, are also presented. In addition to the purely MC-relatedstudies, a comparison is made between the MC, drift-diffusion,and energy-balance methods for simulation of verticalMESFETs.</p><p>The bulk transport properties of electrons in 2H-, 3C-, 4H-and 6H-SiC are studied. For high electric fields the driftvelocity, and carrier mean energy are presented as functions ofthe field. For 4H-SiC impact-ionization coefficients,calculated with a detailed quantum-mechanical model ofband-to-band tunneling, are presented. Additionally, a study oflow-field mobility in 4H-SiC is presented, where the importanceof considering the neutral impurity scattering, also at roomtemperature, is pointed out.</p><p>The properties of 4H- and 6H-SiC when used in short-channelMOSFETs, assuming a high quality semiconductor-insulatorinterface, are investigated using a simple model for scatteringin the semiconductor-insulator interface. Furthermore, theeffect is studied on the low and high-field surface mobility,of the steps formed by the common off-axis-normal cutting ofthe 4H- and 6H-SiC crystals. In this study an extension of theprevious-mentioned simple model is used.</p>

<p>Silicon carbide rectifiers are commercially available since 2001, and MESFET switches are expected to enter the market within a year. Moreover, three inch SiC wafers can be purchased nowadays without critical defects for the device performance and four inch substrate wafers are announced for the year 2005. Despite this tremendous development in SiC technology, the reliability issues like device degradation or high channel mobility still remain to be solved.</p><p>This thesis focuses on SiC surface passivation and termination, a topic which is very important for the utilisation of the full potential of this semiconductor. Three dielectrics with high dielectric constants, Al2O3, AlN and TiO2, were deposited on SiC with different techniques. The structural and electrical properties of the dielectrics were measured and the best insulating layers were then deposited on fully processed and well characterised 1.2 kV 4H SiC PiN diodes. For the best Al2O3 layers, the leakage current was reduced to half its value and the breakdown voltage was extended by 0.5 kV, reaching 1.6 kV, compared to non passivated devices.</p><p>As important as the proper choice of dielectric material is a proper surface preparation prior to deposition of the insulator. In the thesis two surface treatments were tested, a standard HF termination used in silicon technology and an exposure to UV light from a mercury lamp. The second technique is highly interesting since a substantial improvement was observed when UV light was used prior to the dielectric deposition. Moreover, UV light stabilized the surface and reduced the leakage current by a factor of 100 for SiC devices after 10 Mrad γ ray exposition. The experiments indicate also that the measured leakage currents of the order of pA are dominated by surface leakage.</p>

<p>Silicon Carbide (SiC) is a wide band-gap semiconductor material with excel-lent material properties for high frequency, high power and high temperature elec-tronics. In this work different SiC field-effect transistors have been studied using theoretical methods, with the focus on both the devices and the methods used. The rapid miniaturization of commercial devices demands better physical models than the drift-diffusion and hydrodynamic models most commonly used at present.</p><p>The Monte Carlo method is the most accurate physical methods available and has been used in this work to study the performance in short-channel SiC field-effect devices. The drawback of the Monte-Carlo method is the computational power required and it is thus not well suited for device design where the layout requires to be optimized for best device performance. One approach to reduce the simulation time in the Monte Carlo method is to use a time-domain drift-diffusion model in contact and bulk regions of the device. In this work, a time-domain drift-diffusion model is implemented and verified against commercial tools and would be suitable for inclusion in the Monte-Carlo device simulator framework.</p><p>Device optimization is traditionally performed by hand, changing device pa-rameters until sufficient performance is achieved. This is very time consuming work without any guarantee of achieving an optimal layout. In this work a tool is developed, which automatically changes device layout until optimal device per-formance is achieved. Device optimization requires hundreds of device simulations and thus it is essential that computationally efficient methods are used. One impor-tant physical process for RF power devices is self heating. Self heating can be fairly accurately modeled in two dimensions but this will greatly reduce the computa-tional speed. For realistic influence self heating must be studied in three dimensions and a method is developed using a combination of 2D electrical and 3D thermal simulations. The accuracy is much improved by using the proposed method in comparison to a 2D coupled electro/thermal simulation and at the same time offers greater efficiency. Linearity is another very important issue for RF power devices for telecommunication applications. A method to predict the linearity is imple-mented using nonlinear circuit simulation of the active device and neighboring passive elements.</p>

The properties of free-standing cubic silicon carbide for optoelectronic applications are explored in this work. The main focus of the work is on boron doped cubic silicon carbide, which is proposed as a highly useful material in several optoelectronic applications. The material is grown using sublimation epitaxy and the doped material is grown homoepitaxially on nominally undoped seeds. It is characterized using the experimental setups of photoluminescence spectroscopy, Nomarski interference spectroscopy and absorption spectroscopy. I have studied seed growth of nominally undoped cubic material on hexagonal (4H) substrates, and the influence on the grown material from the different faces of the substrate. It is found that it is not possible under the explored conditions to completely cover the growth area with the cubic polytype on the carbon face, but it can be done reproducibly on the silicon face. Reasons for this are discussed. Different doping setups are also explored. The influence on the material properties from growth conditions is explored. It is shown from absorption measurements that it is possible to grow boron doped cubic silicon carbide using this growth method, whereas optical microscopy studies show that the sample quality degrades with high doping concentrations. I have explored the luminescence properties of the material. No boron related emission is found with either room temperature or low temperature photoluminescence spectroscopy. Reasons for this are discussed using results from absorption measurements and optical microscopy.

Increasing oil prices and concerns about global warming have reinforced the interest in biofuels for domestic and district heating, most commonly through combustion of solid biomass like wood logs, hog fuel and pellets. Combustion at non-optimal conditions can, however, lead to substantial emissions of noxious compounds like unburned hydrocarbons, carbon monoxide, and nitrogen oxides as well as the generation of soot. Depending on the rate of combustion more or less air is needed per unit time to completely oxidize the fuel; deficiency of air leading to emissions of unburned matter and too much of excess air to slow combustion kinetics and emissions of mainly carbon monoxide. The rate of combustion is influenced by parameters like fuel quality – moisture and ash content etc. – and in what phase the combustion takes place (in the gas phase through combustion of evaporated substances or on the surface of char coal particles), none of which is constant over time. The key to boiler operation, both from an environmental as well as a power to fuel economy point of view, is thus the careful adjustment of the air supply throughout the combustion process. So far, no control schemes have been applied to small-scale combustors, though, mainly due to the lack of cheap and simple means to measure basic flue gas parameters like oxygen, total hydrocarbon, and carbon monoxide concentrations. This thesis reports about investigations on and characterization of silicon carbide (SiC) based Metal Insulator Semiconductor (MIS) field effect gas sensors regarding their utility in emissions monitoring and combustion control applications as well as the final development of a sensor based control system for wood fired domestic heating systems. From the main sensitivity profiles of such sensor devices, with platinum (Pt) and iridium (Ir) as the catalytic metal contacts (providing the gas sensing ability), towards some typical flue gas constituents as well as ammonia (NH3), a system comprising four individual sensors operated at different temperatures was developed, which through the application of Partial Least Squares (PLS) regression, showed good performance regarding simultaneous monitoring of propene (a model hydrocarbon) and ammonia concentrations in synthetic flue gases of varying content. The sensitivity to CO was, however, negligible. The sensor system also performed well regarding ammonia slip monitoring when tested in real flue gases in a 5.6 MW boiler running SNCR (Selective Non-Catalytic reduction of nitrogen oxides with ammonia). When applied to a 200 kW wood pellet fuelled boiler a similar sensor system was, however, not able to follow the flue gas hydrocarbon concentration in all encountered situations. A PCA (Principal Components Analysis) based scheme for the manipulation of sensor and flue gas temperature data, enabling monitoring of the state of combustion (deficiency or too much of excess air), was however possible to develop. The discrepancy between laboratory and field test results was suspected and later on shown to depend on the larger variation in CO and oxygen concentrations in the flue gases as compared to the laboratory tests. Detailed studies of the CO response characteristics for Pt gate MISiC sensors revealed a highly non-linear sensitivity towards CO, a large response only encountered at high CO/O2 ratios or low temperatures. The response exhibits a sharp switch between a small and a large value when crossing a certain CO/O2 ratio at constant operating temperature, correlated to the transition from an oxygen dominated to an almost fully CO covered Pt surface, originating from the difference in adsorption kinetics between CO and O2. Indications were also given pointing towards an increased sensitivity to background hydrogen as being the mediator of at least part of the CO response. Some general characteristics regarding the response mechanism of field effect sensors with differently structured metal contacts were also indicated. The CO response mechanism of Pt metal MISiC sensors could also be utilized in developing a combustion control system based on two sensors and a thermocouple, which when tested in a 40 kW wood fired boiler exhibited a good performance for fuels with extremely low to normal moisture content, substantially decreasing emissions of unburned matter.

Graphene is one of the most popular material due to its promising properties, for instance electronics applications. Graphene films were grown on silicon carbide (SiC) substrate using chemical vapor deposition (CVD). Influence of the deposition temperature on the morphology of the films was investigated. Characterizations were done by reflectance mapping, atomic force microscopy and Raman spectroscopy. Two samples were done by sublimation process, to compare the number of layers and the morphology of the graphene films with the one grown by chemical vapor deposition.The reflectance mapping showed that the number of layers on the samples made by CVD was notinfluenced by the deposition temperature. But also, demonstrated that sublimation growth is present in allthe samples due to the presence of silicon coating in the susceptor. The growth probably started by sublimation and then CVD deposition. The step morphology characteristic of the silicon carbide substrate surface was conserved during the deposition of graphene. But due to surface step bunching, a decrease inthe step height occurred and the width of the terraces increased. The decreasing in deposition temperature leads to a smoother surface with the CVD method. Raman spectroscopy confirmed the presence ofgraphene and of the buffer layer characteristic of the sublimation growth. Moreover, it demonstrated the presence of compressive strain in the graphene layers.

<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p> / Dissertation