Thesis (Ph.D.) - Carleton University, 2007. / Includes bibliographical references (p. 194-201). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 82-92). Also available in electronic format on the Internet.

Typescript. Includes bibliographical references.

Thesis (doctoral)--VTT Micronova, 2006. / Includes bibliographical references. Also available on the World Wide Web.

abstract: High-Resistivity Silicon (HRS) substrates are important for low-loss, high-performance microwave and millimeter wave devices in high-frequency telecommunication systems. The highest resistivity of up to ~10,000 ohm.cm is Float Zone (FZ) grown Si which is produced in small quantities and moderate wafer diameter. The more common Czochralski (CZ) Si can achieve resistivities of around 1000 ohm.cm, but the wafers contain oxygen that can lead to thermal donor formation with donor concentration significantly higher (~1015 cm-3) than the dopant concentration (~1012-1013 cm-3) of such high-resistivity Si leading to resistivity changes and possible type conversion of high-resistivity p-type silicon. In this research capacitance-voltage (C-V) characterization is employed to study the donor formation and type conversion of p-type High-resistivity Silicon-On-Insulator (HRSOI) wafers and the challenges involved in C-V characterization of HRSOI wafers using a Schottky contact are highlighted. The maximum capacitance of bulk or Silicon-On-Insulator (SOI) wafers is governed by the gate/contact area. During C-V characterization of high-resistivity SOI wafers with aluminum contacts directly on the Si film (Schottky contact); it was observed that the maximum capacitance is much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and the buried oxide capacitance. In addition, an "S"-shape C-V plot was observed in the accumulation region. The effects of various factors, such as: frequency, contact and substrate sizes, gate oxide, SOI film thickness, film and substrate doping, carrier lifetime, contact work-function, temperature, light, annealing temperature and radiation on the C-V characteristics of HRSOI wafers are studied. HRSOI wafers have the best crosstalk prevention capability compared to other types of wafers, which plays a major role in system-on-chip configuration to prevent coupling between high frequency digital and sensitive analog circuits. Substrate crosstalk in HRSOI and various factors affecting the crosstalk, such as: substrate resistivity, separation between devices, buried oxide (BOX) thickness, radiation, temperature, annealing, light, and device types are discussed. Also various ways to minimize substrate crosstalk are studied and a new characterization method is proposed. Owing to their very low doping concentrations and the presence of oxygen in CZ wafers, HRS wafers pose a challenge in resistivity measurement using conventional techniques such as four-point probe and Hall measurement methods. In this research the challenges in accurate resistivity measurement using four-point probe, Hall method, and C-V profile are highlighted and a novel approach to extract resistivity of HRS wafers based on Impedance Spectroscopy measurements using polymer dielectrics such as Polystyrene and Poly Methyl Methacrylate (PMMA) is proposed. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

Silicon-on-insulator (SOI) technology has become increasingly attractive because of the strong light confinement, which significantly reduces the footprint of the photonic components, and the possibility of monolithically integrating advanced photonic waveguide circuits with complex electronic circuits, which may reduce the cost of photonic integrated circuits by mass production. This thesis is dedicated to numerical simulation and experimental performance measurement of passive SOI waveguide devices. The thesis consists of two main parts. In the first part, SOI curved waveguide and corner turning mirror are studied. Propagation losses of the SOI waveguide devices are accurately measured using a Fabry-Perot interference method. Our measurements verify that the SOI corner turning mirror structures can not only significantly reduce the footprint size, but also reduce the access loss by replacing the curved sections in any SOI planar lightwave circuit systems. In the second part, an optical 90o hybrid based on 4 × 4 multimode interference (MMI) coupler is studied. Its quadrature phase behavior is verified by both numerical simulations and experimental measurements.

abstract: Combining the rapid development of semiconductor technologies, miniaturization of integrated circuits (ICs), and scaling down the device size is trending towards faster, cheaper, and more reliable components for low-power integrated circuits. Most research and development relate to efficiency, structure, materials, and performance. However, the thermal problem is also created and becomes more critical with shrinking device dimensions and increased integration densities, such that it affects the device performance and leads to degradation and damage. At the nanometer scale, the self-heating effect (SHE) is one of the main factors to degrade devices. Therefore, tracking and quantifying the SHE is important for reliability and efficiency issues. In this dissertation, engineers design two identical and closely spaced 40nm gate length silicon-on-insulator (SOI) n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) that share a common source with the same active silicon region. One of the MOSFETs acts as a heater to heat-up the active region, while the other one is a thermometer to evaluate the SHE and local temperature changes. The thermometer provides a method to calibrate the numerical models of self-heating and track the heat flow. Moreover, it also involves a trap-rich SOI wafer technology, in which a trap-rich layer, with higher resistivity and lower thermal conductivity compared to conventional bulk silicon substrates. The trap-rich SOI substrates can reduce the cross-talk and minimize the power consumption to increase the system performance. In particular, it offers a solution to radio frequency integrated circuits (RFICs) which require fast switching and low leakage. In high power amplifier (PA) applications, Watt-level PAs operates at less than 50% efficiency because of temperature limitations. The author uses experimental measurements of the local temperature changes, combined with simulations to examine the heat flow and temperature distribution. The approach may be useful to build a self-test application, because it can quantify the temperature changes by putting one or multiple NMOSFET thermometers around a complementary metal-oxide-semiconductor (CMOS) power amplifier, while only adding minimum die area. It points to ways in which it can optimize the reliability of RFIC applications, which operate under high-temperature or high-power conditions to protect the device before it is overheated or damaged. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

Orientador: Maria Glória Caño de Andrade / Resumo: Este trabalho é baseado no estudo do comportamento de um diodo PIN de multicamadas utilizado como célula solar. Esse estudo é desenvolvido por meio de simulações em ambiente virtual, validada a partir de dados experimentais, e tem como foco principal o comportamento da geração de corrente pelo dispositivo, tanto na interação entre o dispositivo e uma determinada faixa do espectro luminoso, como na influência que as alterações nas dimensões dessa célula solar podem trazer na tensão gerada. O diodo PIN proposto encontra-se em uma lâmina SOI (Silicon On Insulator) com uma potencial aplicação destinada para a alimentação de circuitos que necessitam de ultrabaixa potência (ULP – Ultra Low Power), tais como sensores de campo para monitoramento e circuitos subcutâneos para monitoramento médico. É construído por uma camada dupla com diferentes semicondutores (silício e germânio) e, através de alterações em sua estrutura (mudança dos materiais e das dimensões), será verificado o comportamento dos principais parâmetros de uma célula solar, tais como fator de forma (FF), corrente fotogerada, tensão de circuito aberto, corrente de curto-circuito, tensão e corrente de trabalho e potência gerada pelo dispositivo. Adicionalmente, é também analisado o comportamento de penetração e absorção do espectro luminoso na célula solar e a existência de alterações nos parâmetros medidos quando há alteração na posição das camadas de semicondutores, com a finalidade de demonstrar que o incremento de uma... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: This work is based on the study of multilayer PIN diode used as a solar cell. This study was developed through simulations in a virtual environment with the main focus of the generation current by the device so much in the interaction between the device and a range of the light spectrum as well as in the influence the changes in the dimensions of the solar cell may bring in the voltage generated. It is composed of a double layer with different semiconductors (silicon and germanium), and though changes in its structure (materials and dimensions change), it will be verified the behavior of main parameters of a solar cell, such as Fill Factor (FF), photogenerated current, open-circuit voltage, short circuit current, work voltage and work current and the generated power will by the device. Additionally, it was also verified the behavior of the penetration and absorption of the light spectrum in the solar cell, and the existence of changes in the measured parameters when there is a change of position in the semiconductor layers, to demonstrate that the increase of a germanium layer may bring to the device concerning entirely silicon device. The results obtained indicate that there was an increase in the photogeneration when the germanium layer is positioned above the silicon layer. This way, this work demonstrates that small changes in the construction and the thickness of the lateral PIN diode used as a solar cell provide an increase in efficiency of more than 136% when comparing... (Complete abstract click electronic access below) / Mestre

Bends and splitters are typically the fundamental limiting waveguide components in reducing the size of planar lightwave circuits (PLCs) based on waveguides that have a low core/clad refractive index contrast, such as silicon-on-insulator (SOI) rib waveguides. This dissertation presents a solution to this problem in the form of trench-based bends (TBBs) and trench-based splitters (TBSs). Emphasis is placed on experimental demonstration of these components and their integration into practical devices exhibiting significant size reduction. First, a compact and low loss silicon-on-insulator rib waveguide 90◦ TBB is demonstrated based on an etched vertical interface and total internal reflection (TIR) realized by a trench filled with SU8. The measured loss for TE polarization is 0.32 dB ± 0.02 dB/bend at a wavelength of 1.55 μm, which is the best reported in literature. Next, 90◦ TBSs are reported in which each splitter occupies an area of only 11 μm x 11 μm. These components require fabrication of trenches with a nearly 10:1 aspect ratio. A variety of single TBSs are fabricated having different trench widths. The relative amount of power directed into the transmission and reflection arms of the splitters is measured. The TBS reflection and transmission ratio agrees with three dimensional (3D) finite difference time domain (FDTD) predictions. An 82 nm wide trench filled with index matching fluid is experimentally shown to have a reflection/transmission splitting ratio of 49/51 at a wavelength of 1550 nm. To increase the fabrication yield of TBSs, the splitter angle is modified from 90◦ to 105◦, which permits the trench width to be increased to 116 nm for a 50/50 splitter using SU8 as the trench fill material. The fabrication and measurement of compact 105◦ TBBs and TBSs are reported followed by their integration into 1 x 4, 1 x 8, and 1 x 32 trench-based splitter networks (TBSNs). The measured total optical loss of the 1 x 32 TBSN is 9.15 dB. Its size is only 700 μm x 1600 μm for an output waveguide spacing of 50 μm. Finally, a compact SOI trench-based ring resonator (TBRR) composed of 90◦ TBBs, TBSs, and rib waveguides is demonstrated. A TBRR with a ring circumference of 50 μm occupies an area of 20 x 20 μm. The free spectral range (FSR) is as large as 14 nm. By changing the trench fill material from SU8 (n = 1.57) to index fluid (n = 1.733), the peak wavelength can be shifted ∼2 nm. Fabricated TBSNs and TBRRs demonstrate that large size reductions are possible for devices based on TBBs and TBSs. The net result is bend and splitter configurations with a size that is essentially independent of core/clad refractive index contrast. The approach developed in this dissertation is applicable to a wide range of waveguide material systems that have small core/clad refractive index contrast.

The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated. Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary. This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms. / Master of Science