Master of Science / Department of Electrical Engineering / William B. Kuhn / Designers of mixed-signal systems must understand coupling mechanisms at the system, PC board, package and integrated circuit levels to control crosstalk, and thereby minimize degradation of system performance. This research examines coupling mechanisms in a RF-targeted high-resistivity partially-depleted Silicon-on-Insulator (SOI) IC process and applying similar coupling mitigation strategies from higher levels of design, proposes techniques to reduce coupling between sub-circuits on-chip. A series of test structures was fabricated with the goal of understanding and reducing the electric and magnetic field coupling at frequencies up to C-Band. Electric field coupling through the active-layer and substrate of the SOI wafer is compared for a variety of isolation methods including use of deep-trench surrounds, blocking channel-stopper implant, blocking metal-fill layers and using substrate contact guard-rings. Magnetic coupling is examined for on-chip inductors utilizing counter-winding techniques, using metal shields above noisy circuits, and through the relationship between separation and the coupling coefficient. Finally, coupling between bond pads employing the most effective electric field isolation strategies is examined. Lumped element circuit models are developed to show how different coupling mitigation strategies perform. Major conclusions relative to substrate coupling are 1) substrates with resistivity 1 kΩ·cm or greater act largely as a high-K insulators at sufficiently high frequency, 2) compared to capacitive coupling paths through the substrate, coupling through metal-fill has little effect and 3) the use of substrate contact guard-rings in multi-ground domain designs can result in significant coupling between domains if proper isolation strategies such as the use of deep-trench surrounds are not employed. The electric field coupling, in general, is strongly dependent on the impedance of the active-layer and frequency, with isolation exceeding 80 dB below 100 MHz and relatively high coupling values of 40 dB or more at upper S-band frequencies, depending on the geometries and mitigation strategy used. Magnetic coupling was found to be a strong function of circuit separation and the height of metal shields above the circuits. Finally, bond pads utilizing substrate contact guard-rings resulted in the highest degree of isolation and the lowest pad load capacitance of the methods tested.

Silicon-on-insulator (SOI) technology has become increasingly attractive because of the strong light confinement, which significantly reduces the footprint of the photonic components, and the possibility of monolithically integrating advanced photonic waveguide circuits with complex electronic circuits, which may reduce the cost of photonic integrated circuits by mass production. This thesis is dedicated to numerical simulation and experimental performance measurement of passive SOI waveguide devices. The thesis consists of two main parts. In the first part, SOI curved waveguide and corner turning mirror are studied. Propagation losses of the SOI waveguide devices are accurately measured using a Fabry-Perot interference method. Our measurements verify that the SOI corner turning mirror structures can not only significantly reduce the footprint size, but also reduce the access loss by replacing the curved sections in any SOI planar lightwave circuit systems. In the second part, an optical 90o hybrid based on 4 × 4 multimode interference (MMI) coupler is studied. Its quadrature phase behavior is verified by both numerical simulations and experimental measurements.

We have investigated the structure and interfacial structure of two types of high-k dielectric thin films on Si using combined experimental and theoretical approaches. In the Hf-based high- k dielectrics, the crystallinity of three films, pure HfO2, Y-incorporated HfO2 and Al-incorporated HfO2, is examined by transmission electron diffraction (TED), and the local coordination symmetries of the Hf atoms in the films are revealed by the profile of electron energy-loss near-edge structure (ELNES) taken at oxygen K-edge. These ELNES spectra are then simulated using real-space multiple-scattering (RSMS) method. We find a good agreement between the experimental and the simulated result of pure HfO2. The incorporation of Y indeed stabilizes HfO 2 to a cubic structure, but it also contributes to possible lattice distortion and creation of complex defect states, causing discrepancies between the experimental and the simulated result. As a comparison, the local coordination symmetry of Hf is largely degraded upon the incorporation of Al, which not only amorphorizes HfO2, but also introduces significantly amount of O vacancies in the film. We have further investigated the interfacial structures of HfO2 and Al-incorporated HfO2 thin films on Si using spatially resolved ELNES, which a series of the oxygen K-edge spectra is acquired when a 0.3 nm electron probe scanning across the film/Si interface. We find that interfaces are not atomically sharp, and variation in the local coordination symmetry of Hf atoms lasts for a couple of monolayers for both the HfO2 and the Al-incorporated HfO2 samples. Annealing of the HfO2 film in the oxygen environment leads to the formation of a thick SiO2/SiOx stack layer in-between the original HfO2 and the Si substrate. As a comparison, the interfacial stability is significantly improved by incorporating Al into the HfO 2 film to form HfAlO, which effectively reduces/eliminates the interfacial silicon oxide formation during the oxygen annealing process. The interfacial structure of SiTiO3 (STO) dielectric and Si is significant different from that between Hf-based dielectric and Si, as the crystalline STO is epitaxially grown on the Si. Together with the high resolution high-angle annular-dark-field (HAADF) image, the spatially resolved ELNES acquired across the STO/Si interface reveal an amorphous interfacial region of 1-2 monolayer thickness, which is lack of Sr, but contains Ti, Si, and O. Based on these experimental evidences, we propose a classical molecular dynamic (MD) interface model, in which the STO is connected to Si by a distorted Ti-O layer and a complex Si-O layer. The simulated results, based on the MD interface model, generally agree with the experimental results, disclosing a gradual change of the local atomic coordination symmetry and possible defect incorporation at the interface. / Wang, Xiaofeng = Si衬底上高k介电薄膜的结构研究 / 王晓峰. / Adviser: Li Quan. / Source: Dissertation Abstracts International, Volume: 72-11, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves 103-112). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Wang, Xiaofeng = Si chen di shang gao k jie dian bo mo de jie gou yan jiu / Wang Xiaofeng.

Liang Tak-keung. / "June 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

This thesis describes the development and demonstration of a new technique for the fabrication of well-defined quantum dots in a bulk silicon substrate, for potential applications such as quantum computation in coupled quantum dots. Hall characterisation was performed on double-gated mesaMetal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) on a silicon-on-insulator (SOI) substrate, for the purpose of silicon quantum dots in etched nanowires on SOI. Carrier density and mobility results are presented, demonstrating top- and backgate control over the two inversion layers created at the upper and lower surfaces of the superficial silicon mesa. A new technique is developed enabling effective depletion gating of quantum dots in a bulk silicon substrate. A lower layer of aluminium gates is defined using electron beam lithography; the surface of these gates is oxidised using a plasma oxidation technique; and a further layer of aluminium gates is deposited. The lower gates form tunable tunnel barriers in the narrow inversion layer channel created by the upper MOSFET gate. The two layers of gates are electrically isolated by the localised layer of aluminium oxide. Low-temperature transport spectroscopy has been performed in both the many electron (∼100 electrons) and the few electron (∼10 electrons) regimes.Excited states in the bias spectroscopy provide evidence of quantum confinement. Preliminary temperature and magnetic field dependence data are presented. These results demonstrate that depletion gates are an effective technique for defining quantum dots in silicon. Furthermore, the demonstration of the first silicon radio-frequency single electron transistor is reported. The island is again defined by electrostatically tunable tunnel barriers in a narrow channel field effect transistor. Charge sensitivities of better than 10μe/√Hz are demonstrated at MHz bandwidth. These results establish that silicon may be used to fabricate fast, sensitive electrometers.

The conventional large radii bends used in large cross section silicon-on-insulator waveguides were replaced with novel wet etched corner mirrors, potentially allowing much smaller devices, therefore lower costs. If such corners had been based on reactive ion etch techniques they would have had the disadvantage of rougher surfaces and poor alignment in the vertical direction. Wet etching overcomes these two problems by providing smooth corner facets aligned precisely to the vertical {100} silicon crystallographic planes. The waveguides obtained had angled walls, and so numerical analysis was undertaken to establish the single mode condition for such trapezoidal structures. To show the relationship between fabrication tolerances and optical losses a three dimensional simulation tool was developed, based on expansion of the incident mode into plane waves. Various new fabrication techniques were are proposed, namely: the use of titanium as a mask for deep silicon wet anisotropic etching, a technique for aligning masks to the crystal plane on silicon-oninsulator wafers, a corner compensation method for sloping sidewalls, and the suppression of residues and pyramids with the use of acetic acid for KOH etching. Also, it was shown that isopropyl alcohol may be used in KOH etching of vertical walls if the concentration and temperature are sufficiently high. As the proposed corner mirrors were convex structures the problem of undercutting by high order crystal planes arose. This was uniquely overcome by the addition of some structures to effectively convert the convex structures into concave ones. The corner mirrors had higher optical losses than were originally hoped for, similar to those of mirrors in thin film waveguides made by RIE. The losses were possibly due to poor angular precision of the lithography process. The design also failed to provide adequate mechanisms to allow the etch to be stopped at the optimal time. The waveguides had the advantage over thin film technology of large, fibre-compatible cross sections. However the mirror losses must be reduced for the technology to compete with existing large cross section waveguides using large bends. Potential applications of the technology are also discussed. The geometry of the crystal planes places fundamental limits on the proximity of any two waveguides. This causes some increase in the length of MMI couplers used for channel splitting. The problem could possibly be overcome by integrating one of the mirrors into the end of the MMI coupler to form an L shaped junction.

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

The characteristics of a silicon-on-insulator (SOI) rib waveguide, including the bending loss of a multimode bent waveguide and the birefringence of a rib waveguide, are analyzed by using a finite-difference method (FDM). Based on a detailed analysis for a multimode bent waveguide, an appropriately designed multimode bent waveguide for reducing effectively the bending loss of the fundamental mode is realized. The slab height and the rib width of an SOI rib waveguide are normalized with the total height of the silicon layer and a general relation between these two normalized parameters for a nonbirefringent SOI rib waveguide is established. Using this general relation, one can easily design a nonbirefringent SOI rib waveguide. The issue of multimode effect in the SOI-based microphotonic devices such as arrayed-waveguide gratings (AWGs), etched diffraction gratings (EDGs), and multimode interference (MMI) couplers is discussed in detail. Two kinds of taper structures are proposed for reducing the multimode effects in EDGs or MMI couplers. A bi-level taper is introduced to eliminate effectively the multimode effects in an EDG or an MMI coupler. The bi-level taper is very appropriate for an EDG demultiplexer since the Si layer is etched through simultaneously for both the grating and the bottom taper structure, and thus no additional fabrication process is required. For the simulation of an AWG demultiplexer, a fast simulation method based on the Gaussian approximation is proposed and two kinds of effective and accurate three-dimensional (3D) simulation modeling are developed. The first 3D model is based on Kirchhoff-Huygens diffraction formula. To improve the computational speed, the 3D model is reduced to a two-dimensional (2D) one by integrating the corresponding field distributions in the AWG demultiplexer along the vertical direction under an assumption that the power coupled to the higher order modes in the free propagation region (FPR) is negligibly small. The equivalent 2D model has an almost the same accuracy as the original 3D model. Furthermore, a reciprocity theory is introduced for the optimal designof a special structure used for flattening the spectral response of an AWG demultiplexer. In the second 3D simulation method, we combine a beam propagation method (BPM) and the Kirchhoff-Huygens diffraction formula. In this method, a 3D BPM in a polar coordinate system is used for calculating the light propagation in the region connecting the first FPR and the arrayed waveguides, and thus the coupling coefficient of each arrayed waveguide is calculated conveniently and accurately. In the simulation of the second FPR, due to the uniform arrangement of arrayed waveguides, only several arrayed waveguides are needed in the BPM window and thus the computational efficiency is improved. / QC 20101004

Silicon-on-insulator (SOI) technology has become increasingly attractive because of the strong light confinement, which significantly reduces the footprint of the photonic components, and the possibility of monolithically integrating advanced photonic waveguide circuits with complex electronic circuits, which may reduce the cost of photonic integrated circuits by mass production. This thesis is dedicated to numerical simulation and experimental performance measurement of passive SOI waveguide devices. The thesis consists of two main parts. In the first part, SOI curved waveguide and corner turning mirror are studied. Propagation losses of the SOI waveguide devices are accurately measured using a Fabry-Perot interference method. Our measurements verify that the SOI corner turning mirror structures can not only significantly reduce the footprint size, but also reduce the access loss by replacing the curved sections in any SOI planar lightwave circuit systems. In the second part, an optical 90o hybrid based on 4 × 4 multimode interference (MMI) coupler is studied. Its quadrature phase behavior is verified by both numerical simulations and experimental measurements.

Silicon-on-Insulator (SOI) micro-ring resonators (MRRs) are versatile elements in high-density integrated optics telecommunication systems. However, small inaccuracies in the fabrication process intensely deteriorate the response of SOI MRRs. By utilizing the racetrack resonator structures with strong coupling abilities, one can improve the fabrication tolerance. For the SOI racetrack resonators, the FSR is usually large. By introducing gratings into SOI racetrack resonators, the mutual mode coupling between the clockwise and counterclockwise modes can be induced and result in the resonance splitting. The grating-assisted SOI racetrack resonators can increase the operation wavelength and open up the possibility to overcome this limitation. In this thesis, we first use the 2-D FDTD method with the effective index method (EIM) to obtain the transmission spectra of the SOI racetrack resonators. The transmission spectra are then fitted by using the time-domain coupled mode theory (CMT) to obtain the quality factor and optical parameters of the SOI racetrack resonators. Next, we demonstrate the characteristics of mode splitting resulted from the mutual mode coupling between the clockwise and counterclockwise modes in the grating-assisted racetrack resonators by utilizing both the CMT and the 2-D FDTD method with the EIM. By tuning the grating configurations, such as the length or the structure of sidewall gratings, one can obtain the desired transmission spectrum of the grating-assisted racetrack resonators. Finally, we numerically investigate the temperature-dependent spectral characterics of the grating-assisted SOI racetrack resonator by taking the thermal-optic responce of the SOI materials into account. The thermal sensitivity of this device is 95.38 pm/¢XC, and the calculted properties can help the further designs based on the grating-assisted SOI racetrack resonators.