Abstract Anisotropic wet etching is one of the key technologies for the microstructure fabrication in Micro Electro Mechanical Systems (MEMS). Agitation technique is one of the key parameters to affect significantly the quality of silicon anisotropic wet etching, which includes the etch rate and surface roughness. In general, magnetic stirring is used during silicon anisotropic wet etching operation. The ultrasonic agitation and add surfactant have been to replaced and to proceed a series of experiment for KOH solution and TMAH solution in this study. The results show that the ultrasonic agitation can reduce the surface roughness and achieve the high-quality etching surface, its roughness even is only about Ra 47.5Å. Besides, the etch rate is also increased slightly. But it is easily to cause the damage of the microstructure. The addition of anionic surfactant to the KOH solution without any agitation condition can achieve the same at the etching performance of the ultrasonic agitation. The addition of anionic surfactant and nonionic surfactant to the TMAH solution without any agitation condition can achieve the same at the etching performance of the ultrasonic agitation. TMAH solution adds nonionic surfactant not only improves the surface roughness, but also retards the phenomenon of the undercut. Keyword¡Ganisotropic wet etching, magnetic stirring, ultrasonic, surfactant

Abstract The high-speed performance of the lump-type electroabsorption modulator (EAM) is mainly limited by RC-effect. By taking advantage of the distributive effects, the traveling-wave structure can overcome the RC-lump effect. However, in order to enhance the limitation imposed by the conventional slow-waveguide type of traveling-wave structure, the speed of the device is still mainly restricted by the distributed capacitance of the waveguide. In this work, a novel type of traveling-wave-electroabsorption-modulator based on the undercut-etching the active region is successfully fabricated and measured. The methods of the processing adopted here is to lower the capacitance by chemical-wet-etching and two-time subsequent undercut etching on active region to further decrease the parasitic capacitance between P-type and N-type cladding layer. Also, the optical scattering loss may be reduced due the smooth sidewall of the waveguide from the wet etching. The whole processing shown in this thesis includes the lift-off technique by lithography, the metalization for n-, p- contacts (by thermal evaporator) and CPW microwave transmission (by e-beam evaporator), and PMGI-planarization. ¡V15dB optical transmission, ¡V6dB electrical transmission loss and >20GHz 3dB bandwidth of electrical-to-optical response at 50£[termination is measured on this kind of devices. It exhibits a high potential on the application of high-speed optical-fiber link in the future.

The purpose of this thesis is to fabricate 12-layer In0.75Ga0.25As quantum dot-in-a-well (In0.1Ga0.9As) structures grown by molecular-beam epitaxy (MBE) on GaAs substrate, and analyze the optical properties of laser devices for optical fiber communication systems. For the laser structures, larger Al content AlGaAs cladding layer enhance the optical confinement, but encounter much challenges to improve the quality. After we simulate and fabricate different Al content laser structures, we find the best cladding layer composition - Al0.2Ga0.8As which performs a best material gain. In the active layer, 12 layers In0.75Ga0.25As quantum dots (QDs) and QDs in a well (DWell) structure, and DWell with Be-doping in the well structure are included in this study. The well structure slows down the hot carriers speed and Be-doping decrease the carrier life time and increases the electron-hole pair recombination rate. We increase the QDs deposition coverage to move the emission wavelength to 1.3£gm, but the high temperature cladding layer growth process indirectly anneal the QDs and result in the emission wavelength blue shift to 1.24£gm. In the laser fabrication, to transport the light wave in smaller dispersion loss single mode waveguide, wet etching photolithography processes are adapted in this study to fabricate 2£gm width ridge waveguide. The as-cleaved facets are used as Fabry-Perot laser mirrors in ridge waveguide lasers. Finally, the current density of QD Laser(C528) lasing in CW mode is 581A/cm2, slope efficiency of 510mW/A and maximum power/facet of 65mW are obtained.Then the current density of DWELL+PD Laser(C540) lasing in CW mode is 880A/cm2, slope efficiency of 430mW/A and maximum power/facet of 34mW are obtained.

A simple and high efficient wet etching technique for fabricating pyramid textures on (100) Si wafer is proposed. Conventionally, pyramid textures were formed on Si wafers to reduce reflections using KOH anisotropic etching. Isopropyl Alcohol (IPA) is often added to the solution to abate the bubbling effect caused by hydrogen released form the Si surfaces during reaction. In this study, a metal net with proper opening dimension was used as a shelter to trap the hydrogen from leaving the surfaces of Si, and therefore turns the hydrogen gas into a gas-type etching mask during the anisotropic etching. In this way, pyramid textures with dimensions range from 3µm to 8µm were successfully fabricated. The measured average reflectivity of the texture for incident optical wave length from 400nm to 1000nm is less than 18%.

Continuous scaling down of the dimensions of electronic devices has made present day computers more powerful. In the front end of line, the minimum lateral dimensions in a transistor have shrunk from 45 nm in 2007 to 22 nm currently, and the gate oxide film thickness is two to three monolayers. This reduction in dimensions makes surface preparation an increasingly important part of the device fabrication process. The atoms or molecules that terminate surfaces function as passivation layers, diffusion barriers, and nucleation layers. In the back end of line, metal layers are deposited to connect transistors. We demonstrate a reproducible process that deposits a monolayer of aminopropyltrimethoxysilane molecules less than one nanometer thick on a silicon dioxide surface. The monolayer contains a high density of amine groups that can be used to deposit Pd and Ni and subsequently Co and Cu to serve as the nucleation layer in an electroless metal deposition process. Because of the shrinking device dimensions, there is a need to find new transistor channel materials that have high electron mobilities along with narrow band gaps to reduce power consumption. Compound III--V channel materials are candidates to enable increased performance and reduced power consumption at the current scaled geometries. But many challenges remain for such high mobility materials to be realized in high volume manufacturing. For instance, low defect density (1E7 /cm²) III--V and Ge on Si is the most fundamental issue to overcome before high mobility materials become practical. Unlike Si, dry etching of III-V semiconductor surfaces is believed to be difficult and uncontrollable. Therefore, new wet etching chemistries are needed. Si has been known to passivate by etching in hydrofluoric acid, but similar treatments on III--Vs are known to temporarily hydrogen passivate the surfaces. However, any subsequent exposure to the ambient reoxidizes the surface, resulting in a chemically unstable and high defect density interface. This work compares old and new wet etching chemistries and investigates new methods of passivating the III--V semiconductors.

A Corner Cube Retro-reflector (CCR) is a device that can be used as transmitters in wireless free space optical communication systems, or remote sensing instruments. A novel approach to fabricate the CCR is developed, where almost 100% of the planar chip area acts as the CCR compared to the maximum of 33% in the prior MEMS CCRs. Unlike the conventional micro machined CCRs that have two planes (mirrors of the CCR) normal to the surface of the wafer, our approach yields all the mirrors within the bulk of the wafer, ensuring very high packing densities and wide acceptance angles. The crystallography of single crystal silicon wafer along with different micromachining and wafer bonding techniques are used to fabricate and assemble the CCR. The solid models of both the active and passive CCRs were built using Coventorware simulation software. In the active CCRs, one of the mirror was electrostatically actuated; this is simulated using the software. The results which show a three fold decrease in the pull-in voltage as compared to surface micromachined cantilevers with the same dimensions as presented. Fabrication of the passive CCR along with various fabrication and assembling processes used are discussed. Experimental results are presented and then discussed.

The conventional large radii bends used in large cross section silicon-on-insulator waveguides were replaced with novel wet etched corner mirrors, potentially allowing much smaller devices, therefore lower costs. If such corners had been based on reactive ion etch techniques they would have had the disadvantage of rougher surfaces and poor alignment in the vertical direction. Wet etching overcomes these two problems by providing smooth corner facets aligned precisely to the vertical {100} silicon crystallographic planes. The waveguides obtained had angled walls, and so numerical analysis was undertaken to establish the single mode condition for such trapezoidal structures. To show the relationship between fabrication tolerances and optical losses a three dimensional simulation tool was developed, based on expansion of the incident mode into plane waves. Various new fabrication techniques were are proposed, namely: the use of titanium as a mask for deep silicon wet anisotropic etching, a technique for aligning masks to the crystal plane on silicon-oninsulator wafers, a corner compensation method for sloping sidewalls, and the suppression of residues and pyramids with the use of acetic acid for KOH etching. Also, it was shown that isopropyl alcohol may be used in KOH etching of vertical walls if the concentration and temperature are sufficiently high. As the proposed corner mirrors were convex structures the problem of undercutting by high order crystal planes arose. This was uniquely overcome by the addition of some structures to effectively convert the convex structures into concave ones. The corner mirrors had higher optical losses than were originally hoped for, similar to those of mirrors in thin film waveguides made by RIE. The losses were possibly due to poor angular precision of the lithography process. The design also failed to provide adequate mechanisms to allow the etch to be stopped at the optimal time. The waveguides had the advantage over thin film technology of large, fibre-compatible cross sections. However the mirror losses must be reduced for the technology to compete with existing large cross section waveguides using large bends. Potential applications of the technology are also discussed. The geometry of the crystal planes places fundamental limits on the proximity of any two waveguides. This causes some increase in the length of MMI couplers used for channel splitting. The problem could possibly be overcome by integrating one of the mirrors into the end of the MMI coupler to form an L shaped junction.

This thesis presents the development of electrochemical etch-stop techniques (ECES) to achieve high precision 3-dimensional integrated MEMS sensors with wet anisotropic etching by applying proper voltages to various regions in silicon. The anisotropic etchant is selected as tetra methyl ammonium hydroxide, TMAH, considering its high silicon etch rate, selectivity towards SiO2, and CMOS compatibility, especially during front-side etching of the chip/wafer. A number of parameters affecting the etching are investigated, including the effect of temperature, illumination, and concentration of the etchant over the etch rate of silicon, surface roughness, and biasing voltages. The biasing voltages for passivating the n-well and enhancing the etching reactions on p-substrate are determined as -0.5V and -1.6V, respectively, after a series of current-voltage characteristic experiments. The surface roughness due to TMAH etching is prevented with the addition of ammonium peroxodisulfate, AP. A proper etching process is achieved using a 10wt.% TMAH at 85&deg / C with 10gr/lt. AP. Different silicon etch samples are produced in METU-MET facilities to understand and optimize ECES parameters that can be used for CMOS microbolometers. The etch samples are fabricated using various processes, including thermal oxidation, boron and phosphorus diffusions, aluminum and silicon nitride layer deposition processes. Etching with the prepared samples shows the dependency of the depletion layer between p-substrate and n&amp / #8209 / well, explaining the reason of the previous failures during post-CMOS etching of CMOS microbolometers from the front side. Succesfully etched CMOS microbolometers are achieved with back side etching in 6M KOH at 90 &deg / C, where &amp / #8209 / 3.5V and 1.5V are applied to the p-substrate and n-well. In summary, this study provides an extensive understanding of the ECES process for successful implementations of integrated MEMS sensors.

Evaluation of the wet etching properties of several different thin film oxidesgrown by physical vapour deposition was performed in this work. MgO, Al2O3,SiO2, TiO2, HfO2 ZrO2 and Y2O3 were coated on two types of substrates; Si andborosilicate glass and etching tests were performed in different etchingsolutions. MgF2 thin films have also been evaluated. Important aspects of the choice of the thin films was taken into account in orderto match to good optical properties such as refractive index (n), extinction coefficient (k) and optical thickness (TP) as well as good chemical properties in the wet etching process. A description is made of the physics of optical filters and how a combination of different oxides stacked onto each other can create interference filters. A description of the manufacturing process of the thin films where physical vapour deposition (PVD) was used is presented. Thermal shift of the optical spectra caused by porous coatings was investigated and analyses of the thin films by ellipsometry, surface profilometry and transmission spectrophotometry have been performed. The wet etching properties were evaluated by monitoring the transmission insituon transparent borosilicate glass substrates. A method of how to measure the wet etching rate for different thin films is described. A computer software was used to calculate the Pourbaix diagrams in order to understand the chemical behaviour of the etching solutions. The pH can have a significant impact on the etching behaviour. In case of TiO2, it can be dissolved in an alkaline solution of H2O2. The catalytically process behind this is evaluated. Etching rate for both Y2O3 andSiO2 were matched by adjusting the etchant concentration as a case example. The group IVB oxides are difficult to etch. The catalytic etching of TiO2 with peroxide is slow but detectable. Al2O3, Y2O3 and MgO are reasonably easy to etch but have too low refractive indices to be useful in multilayer optical filters. The In-situ etching instrument was found to be very useful for measuring etching rates. / Utvärdering av våtkemiska egenskaper för flera olika oxidtunnfilmer utfördes idetta arbete på tunnfilmer av MgO, Al2O3, SiO2, TiO2, HfO2 ZrO2 and Y2O3 vakuumdeponerade på både kiselwafers och borosilikatglas. Etstester gjordes med ett flertal etslösningar. Även MgF2-tunnfilmer utvärderades. Både optiska och kemiska egenskaper togs i beaktande vid utvärderingen av tunnfilmerna. De optiska lagar som gäller för tunnfilmer redovisas, bl a hur kombinationer av olika oxider kan skapa interferrensfilter. En beskrivning av tillverkningsprocessen varvid PVD användes presenteras. Termiskt skift av det optiska transmissionsspektrat orsakat av porositet undersöktes. Analyser av tunnfilmerna med ellipsometri, profilometri och transmissions spektroskopi utfördes. Våtetsningsegenskaperna utvärderades genom att mäta in-situ vid etsprocessen på transparenta borosilikatglassubstrat. Metoden för att mäta etshastigheten för olika oxider är beskriven. Datorberäkningar av pourbaixdiagram användes för att skapa en förståelse av de kemiska egenskaperna för etslösningarna. Etsegenskaperna påverkas till stordel av lösningens pH. TiO2 kan etsas i basisk lösning av peroxid. Denna process utvärderades, likaså utvärderades etshasigheten för Y2O3 och SiO2 för att erhålla matchande par avoxider som en fallstudie. Grupp IVB oxiderna är mycket svåra att etsa. Katalytisk etsning av TiO2 med peroxid är detekterbar men långsam. Al2O3, Y2O3 och MgO är förhållandevis enkla att etsa men har för låga brytningsindex för att var praktiskt använbara i optiska multilagerfilter. In-situ etsinstrumentet befanns vara ett utmärkt verktyg för att mäta etshastigheten för tunnfilmer.

In decades, the tremendous development of integrated circuits industry could be mostly attributed to SiO2, since its satisfactory properties as a gate dielectric candidate. The effectivity of SiO2 has been challenged since dielectric layer was scaled down below 3nm, when the gate leakage current of SiO2 became unacceptable. Institution to silicon-based CMOS techniques were proposed, but they have their own limitations. Nowadays, materials with high dielectric constants are mainstream gate dielectric materials in industry, but a SiO2 interfacial layer is still necessary to avoid gap between gate dielectric layer and Si substrate, and to minimize interface trap charges. In this thesis work, by applying lateral heating process on Si wafer with thermally grown ultrathin SiO2, the gate leakage current density could be reduced by 3-5 order of magnitude. MOS capacitors were fabricated, and electrical properties were tested with semiconductor parameter analyzer and LCR meter. The underlying mechanism of this appealing phenomenon was explored. Since unacceptable gate leakage current is one of the main reasons which prevent the scaling trend in semiconductor industry, this technology brings a possibility to post-pone the end of scaling trend, and pave a way for extensive application in industry. A new method for fabrication of MOS capacitors metal gate has been developed, and lift-off process has been replaced by wet etching process. This method provides better contact between dielectric layer and metal gate, meanwhile much easier operation.