Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Silicon interposers with TSVs (through-silicon-vias) have been developed in single-crystalline silicon wafer to achieve the high I/O (Input/Output) density. However, single-crystalline silicon interposers suffer a few problems such as cost, electrical performance and reliability. To overcome these shortcomings, an entirely different approach using polycrystalline silicon interposers with thick polymer liners are proposed by Georgia Tech Packaging Research Center, aiming to achieve lower cost silicon interposers with high performance and reliability. The objective of this research is to explore and demonstrate thin polycrystalline silicon as a suitable interposer material to achieve high performance and high reliability TPVs (through-package-vias) in polycrystalline silicon materials with lower cost. Three fundamental challenges were defined, including: 1) low resistivity of the polycrystalline silicon, resulting in high electrical loss; 2) reliability problems resulting from CTE (coefficient of thermal expansion) mismatch between silicon and Cu, and 3) handling and processing of thin silicon panels. A three-dimensional EM (electromagnetic) model was developed to simulate insertion loss and crosstalk of TPVs and compared with TSVs. It has been shown thick polymer liner is effective in addressing the fundamental challenge of low resistivity for the polycrystalline silicon material, leading to better electrical performance of TPVs than TSVs. Parametric studies indicate that thicker sidewall liners result in better electrical performance. A two-dimensional axisymmetric model was established to simulate the first principal stresses in silicon and shear stresses in TPV under thermal cycling. TPVs with thick polymer liners present both smaller principal stresses and shear stresses than TSVs due to the low modulus of polymer. Parametric studies suggest that sidewall liners act as stress buffers and thicker liners result in better mechanical performance. Design guidelines based on simulation results were used in TPV demonstration and test vehicle fabrication. Fracture strength of polycrystalline silicon panel has been fundamentally studied with four-point bending tool and Weibull plot. Surface polymer liners on both sides were introduced to improve the handling of thin silicon panels. Quantitative study showed higher characteristic fracture strength for the panel with surface liners than raw silicon panel. Low cost and double-side processes have been developed for TPV fabrication including UV (ultraviolet) lasers for TPV formation, double laser method for liner fabrication and electroless Cu for seed formation. Key steps and mechanisms for aforementioned processes were summarized and discussed. Polycrystalline silicon interposers with TPVs and up to four metal RDLs (re-distribution layers) were designed, fabricated and characterized. Measurement results showed low insertion loss for both TPVs and CPW (co-planar waveguide) transmission lines. Good model to hardware correlation was also observed. Reliability test vehicles of polycrystalline silicon interposers were also designed and fabricated for thermal cycling test. TPVs survived 4000 cycles without significant resistance changes. SEM imaging on the cross-section of the samples confirmed no Cu or silicon cracking. Magnified images around corner also suggested good adhesion at Cu/liner and silicon/liner interfaces.

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The reflectivity of crystalline and radiation-damaged silicon carbide and silicon has been measured in the 2-12 eV spectral region. Measurements were made using a standard Seya-Namioka Monochrometer which was modified to compensate for the fluctuations of the light source and interfaced to a micro-computer to facilitate data collection. The reflectivities of crystalline silicon carbide polytypes 6H, 15R, and 4H were found to be similar and the reflectivity of 3C-SiC showed agreement with the predictions of published band structure calculations. The observed reflectivity of radiation damage SiC agreed with the prediction of a simple model which takes into account the breakdown of k(→) -conservation and uses a realistic Bethe-lattice Hamiltonian to calculate the amorphous valence density of electron states.

Currently the cost of solar grade silicon accounts for approximately one third of the total solar cell cost, therefore a new silicon refining process is being proposed with the goal of lowering the cost of producing solar grade silicon. In this new process, Si-Cu alloys were used as the silicon source. One to one molar ratio H2-HCl gas mixtures were used as transport agents to extract Si out from the Si-Cu alloy at about 300-700oC, with following reaction taking place: Si+3HCl(g)=HSiCl3(g)+H2(g) While at about 1000-1300oC, pure Si deposits onto a hot silicon rod according to: Si+3HCl(g)=HSiCl3(g)+H2(g) The role of the copper in the alloy was to trap impurities in the Si and catalyze the gas solid reaction. A study on determining the rate limiting step and impurity behavior was done. A possible silicon extraction reaction mechanism was also addressed.

Currently the cost of solar grade silicon accounts for approximately one third of the total solar cell cost, therefore a new silicon refining process is being proposed with the goal of lowering the cost of producing solar grade silicon. In this new process, Si-Cu alloys were used as the silicon source. One to one molar ratio H2-HCl gas mixtures were used as transport agents to extract Si out from the Si-Cu alloy at about 300-700oC, with following reaction taking place: Si+3HCl(g)=HSiCl3(g)+H2(g) While at about 1000-1300oC, pure Si deposits onto a hot silicon rod according to: Si+3HCl(g)=HSiCl3(g)+H2(g) The role of the copper in the alloy was to trap impurities in the Si and catalyze the gas solid reaction. A study on determining the rate limiting step and impurity behavior was done. A possible silicon extraction reaction mechanism was also addressed.

No description available.

This thesis describes the fabrication of a set of bright, visible light-emitting silicon LEDs. These devices were fabricated in-house at the University of Saskatchewan using a custom plasma ion implantation tool, an annealing furnace, and a physical vapour deposition system. A high-fluence (F = 4 × 1015 cm^−2) implantation of molecular hydrogen ions extracted from an RF inductively coupled plasma at an energy of 5 keV was used to create a heavily damaged region in the silicon centered approximately 40 nm below the silicon surface with a width of approximately 56 nm. A matrix of annealing (e.g. thermal processing) processes at 400 ºC and 700 ºC and different durations (30 minutes and 2 hours) as well as an aluminum gettering procedure were tested with the goal of increasing the output electroluminescence intensity. Current-voltage characterization was used to extract information about the defect-rich nanocrystalline, light-emitting layer as well as the Schottky barrier height. This enabled comparison of these new devices with previous silicon LEDs based on porous silicon and other approaches. The processes which were used to fabricate these devices are compatible with standard CMOS processing techniques and could provide one solution to the problem of optical interconnect on multi-core chips. The scientific significance of this work is the demonstration of bright, visible light emission at mean photon energies ∼1.84 eV corresponding to a photon wavelength of λ ≈ 675 nm. This is remarkable given that ordinary crystalline silicon is an indirect bandgap material with a bandgap energy of 1.1 eV, in which band-to-band radiative recombination is forbidden by momentum conservation. The devices fabricated in this thesis have light emission properties similar to previous silicon LEDs based on nanocrystalline or nanoporous silicon. They have the advantage of being easily electrically driven. The nanocrystalline region which is the source of the light emission was nucleated from the ion-implanted layer below the surface of the silicon. This makes these devices mechanically robust and insensitive to environmental conditions. The engineering significance of this work is the production of CMOS compatible light emitters. This study demonstrated increased light emission efficiency at higher annealing temperatures which is likely due to enhanced diffusion and nucleation of silicon nanocrystals in the ion-implant damaged layer.

This thesis presents an investigation of the phenomenon of efficient, room temperature luminescence from dislocation-engineered (DE) silicon. Previous work had demonstrated that the introduction of near-surface dislocation loops to a silicon substrate by boron ion implantation and high temperature annealing produced efficient electroluminescence at room temperature. However, the mechanism by which high efficiency luminescence is produced was not understood. A wide matrix of specimens containing dislocations was fabricated by a variety of methods, including ion implantation, and their luminescence efficiencies were correlated to their physical properties. Transmission electron microscopy was used to characterise the defect structures created by ion implantation. In the majority of specimens a band of dislocation loops in close proximity to the surface was observed. The dislocation loops were shown to be consistent with a mixture of Frank and perfect dislocation loops, the relative proportions of which were dependent upon processing conditions. The thermal evolution of the dislocation loop size distribution was investigated. For the first time, a size distribution displaying a double peak was observed. The size distribution was shown to be consistent with the Gaussian distribution of two defect populations of different mean diameter. The thermal evolution of the size distribution was investigated in silicon implanted samples. A flux of self-interstitials from Frank dislocation loops to perfect dislocation loops was deduced. The evolution of the dislocation loop sizes was found to be consistent with Ostwald ripening. Cathodoluminescence (CL) was used to investigate the luminescent properties of silicon at room temperature for the first time. A new CL system was installed for this work, initially the CL system was characterised and a routine to ensure a high degree of reproducibility was formed. The luminescence mechanism of DE-silicon was shown to be the same as in unprocessed silicon wafers; TO phonon-assisted recombination. The mechanism of enhanced luminescence from DE-silicon was unambiguously shown to be due to the gettering of electrically active impurities from the specimen bulk. A reduction in the bulk transition metal impurity concentration of up to 35 times was inferred. In samples which were implanted with boron the degree of gettering was found to show a logarithmic dependence on the dislocation density. Using a crosssectional mapping technique, implanted samples were shown to contain a lower concentration of transition metal impurities throughout the entire wafer in comparison to as-received, unprocessed specimens. Furthermore, the impurity concentration was found to be lowest in close proximity to the band of dislocation loops. The dislocation loops were found to act as non-radiative recombination centres and their strength was strongly influenced by the local carrier concentration. The high doping levels of samples implanted with boron were found to minimise the non-radiative recombination action of the dislocations. Low temperature annealing was used to improve the luminescence efficiency of DE-silicon further.

The probability of recombination of photogenerated electron hole pairs in crystalline silicon is governed by the density of surface defect states and the density of charge carriers. Depositions of intrinsic hydrogenated amorphous silicon (a-Si:H) in dc saddle field (DCSF) PECVD system and hydrogenated amorphous silicon nitride (SiNx) in rf PECVD system forms a dual layer stack on c-Si, which results in an excellent passivation of the surface and an anti-reflection coating. Response Surface Methodology is used in this work to optimize the deposition conditions of SiNx. Optimization of the response surface function yielded deposition conditions that materialized in a surface recombination velocity of less than 4cm/s. The BACH (Back Amorphous Crystalline silicon Heterojunction) cell concept makes use of this dual layer a-Si:H/SiNx stack to form a high efficiency photovoltaic device. The high quality passivating structure can result in the BACH solar cell device with more than 20% conversion efficiency.