Abstract The development and advancement of microelectronics industry is very drastically. So, the key to create new technology of process and it's costs can be cut by simulating the performance of these equipments. The reactor of chemical vapor deposition (CVD) is important to semiconductor production process.. This research use numerical method to study the process parameters of low-pressure chemical vapor deposition (LPCVD) of Tungsten (W).In this simulation, the CVD reactor modeling are constructed and discreditzed by using the implicit finite volume method. The grids are arranged in a staggered manner for the discretization of the governing equations. Then, the SIMPLE-type algorithm will be used to solve all of the discretized algebra equations. In this research, the reactor is an single wafer and cold-wall system. The nozzle position is adjustable from 100 to 250mm.The nozzle-to-wafer distance is adjustable by changing the height from 30 to 120mm.The temperature and pressure in the reactor system can be setup with susceptor temperature 300~600 and pressure 0.5~8Torr. The results show that the flow in the reactor may depend on the flow rate and nozzle position. An effective means to avoid unstable is to reduce the susceptor temperature and system pressure due to the effects of buoyancy force and recirculation.

Typical surface preparation consists of exposure to cleaning chemical to remove contaminants followed by rinsing with ultra-pure water which is followed by drying. Large quantities of water, various chemicals, and energy are used during rinsing and drying processes. Currently there is no in-situ metrology available to determine the cleanliness of micro- and nano-structures as these processes are taking place. This is a major technology gap and leads to over use of resources and adversely affects the throughput.Surface preparation of patterned wafers by batch processing becomes a major challenge as semiconductor fabrication moves deeper in submicron technology nodes. Many fabs have already employed single wafer tools. The main roadblock for single-wafer tools is their lower throughput. This obstacle is eased by introduction of multi chamber tools. To reduce cycle time and resource utilization during rinse and dry processes without sacrificing surface cleanliness and throughput, in-situ metrology is developed and used to compare typical single wafer spinning tools with immersion tools for rinsing of patterned wafers. This novel metrology technology includes both hardware for an in-situ measurement and software for process data analysis. Successful incorporation of this metrology will eliminate dependency on external analysis techniques such as Inductively Coupled Mass Spectroscopy (ICPMS), Scanning Electron Microscope (SEM), and Tunneling Electron Microscope (TEM), and will lead to fast response time.In this study the electro-chemical residue sensor (ECRS) was incorporated in a lab scale single-wafer spinning and single- wafer immersion tool. The ECRS was used to monitor dynamics of rinsing of various cleans such as ammonium peroxide mixture (APM), hydrochloric peroxide mixture (HPM), and sulfuric peroxide mixture (SPM). It was observed that different cleaning chemicals impact the subsequent rinse not only through adsorption and desorption but also through surface charge. The results are analyzed by using a comprehensive process model which takes into account various transport mechanisms such as adsorption, desorption, diffusion, convection, and surface charge. This novel metrology can be used at very low concentration with very high accuracy. It is used to study the effect of the key process parameters such as flow rate, spin rate, temperature, and chemical concentration.

Long cycle times in semiconductor manufacturing represent an increasing challenge for the industry and lead to a growing need of break-through approaches to reduce it. Small lot sizes and the conversion of batch processes to mini-batch or single-wafer processes are widely regarded as a promising means for a step-wise cycle time reduction. Our analysis with discrete-event simulation and queueing theory shows that small lot size and the replacement of batch tools with mini-batch or single wafer tools are beneficial but lot size reduction lacks persuasive effectiveness if reduced by more than half. Because the results are not completely convincing, we develop a new semiconductor tool type that further reduces cycle time by lot streaming leveraging the lot size reduction efforts. We show that this combined approach can lead to a cycle time reduction of more than 80%.

Long cycle times in semiconductor manufacturing represent an increasing challenge for the industry and lead to a growing need of break-through approaches to reduce it. Small lot sizes and the conversion of batch processes to mini-batch or single-wafer processes are widely regarded as a promising means for a step-wise cycle time reduction. Our analysis with discrete-event simulation and queueing theory shows that small lot size and the replacement of batch tools with mini-batch or single wafer tools are beneficial but lot size reduction lacks persuasive effectiveness if reduced by more than half. Because the results are not completely convincing, we develop a new semiconductor tool type that further reduces cycle time by lot streaming leveraging the lot size reduction efforts. We show that this combined approach can lead to a cycle time reduction of more than 80%.