This thesis proposes the small signal model for the Interline Power Flow Controller (IPFC). Using this model, the damping performance of the IPFC with different power system configuration is investigated and also compared with the AC Transmission System (FACTS) based controllers such as the Unified Power Flow Controller (UPFC). The IPFC and the UPFC in constant power control mode can be viewed as effectively cutting the connected transmission line. This change on the structure of the network results in a significant change on the small signal stability. This thesis also addresses issues regarding the different levels of models that are required for the investigation of the behavior of FACTS. An effective validation approach that uses a minimum sized demonstration platform is proposed. This platform is small enough for detailed EMTP validation, yet large enough to exhibit the range of transient electrical and electromechanical behavior which is the focus for FACTS devices. To demonstrate the approach, the small signal models of the system embedded with the IPFC and the UPFC are developed respectively. The results obtained from small signal analysis are validated with EMTP-type simulation and show a close agreement.

This thesis proposes the small signal model for the Interline Power Flow Controller (IPFC). Using this model, the damping performance of the IPFC with different power system configuration is investigated and also compared with the AC Transmission System (FACTS) based controllers such as the Unified Power Flow Controller (UPFC). The IPFC and the UPFC in constant power control mode can be viewed as effectively cutting the connected transmission line. This change on the structure of the network results in a significant change on the small signal stability. This thesis also addresses issues regarding the different levels of models that are required for the investigation of the behavior of FACTS. An effective validation approach that uses a minimum sized demonstration platform is proposed. This platform is small enough for detailed EMTP validation, yet large enough to exhibit the range of transient electrical and electromechanical behavior which is the focus for FACTS devices. To demonstrate the approach, the small signal models of the system embedded with the IPFC and the UPFC are developed respectively. The results obtained from small signal analysis are validated with EMTP-type simulation and show a close agreement.

No description available.

In this thesis a buck converter has been developed to be used as a test bench in power electronics laboratory. For this purpose, first, steady-state and small-signal analyses of a buck converter is carried out, then open-loop and closed-loop control of the converter are developed and simulated. Then, the circuit is manufactured and tested. The test results are compared with the simulation results. Finally, an experimantal procedure is prepared to enable the students to perform the experiment in the laboratory with the test bench developed.

In this thesis a boost converter is developed to be used as a test bench in power electronics laboratory. For this purpose, first, steady-state and small-signal analyses of a boost converter are carried out, then closed loop control of the converter is developed and simulated. Then, the circuit is designed and manufactured. The test results are compared with the simulation results. Finally, an experimantal procedure is prepared to enable the students to perform the experiment in the laboratory with the test bench developed.

This thesis presents an investigation into the power transmission limitations imposed on a VSC-HVdc converter by ac system strength and ac system impedance characteristics, quantified by the short circuit ratio (SCR). An important result of this study is that the operation of the converter is not only affected by the SCR’s magnitude, but is also significantly affected by the ac system’s impedance angle at the fundamental frequency. As the ac impedance becomes more resistive, the minimum SCR required at the rectifier side increases from that required for ideally inductive ac impedance, but it decreases at the inverter side. The finite megavolt ampere (MVA) limit of the VSC imposes a further limitation on power transfer, requiring an increase in the value of the minimum SCR. This limitation can be mitigated if additional reactive power support is provided at the point-common-connection. A state-space VSC model was developed and validated with a fully detailed non-linear EMT model. The model showed that gains of the phased-locked-loop (PLL), particularly at low SCRs greatly affect the operation of the VSC-HVdc converter and that operation at low SCRs below about 1.6 is difficult. The model also shows that the theoretically calculated power-voltage stability limit is not attainable in practice, but can be approached if the PLL gains are reduced. The thesis shows that as the VSC-HVdc converter is subject to large signal excitation, a good controller design cannot rely on small signal analysis alone. The thesis therefore proposes the application of optimization tools to coordinate the controls of multiple converters in a dc grid. A new method, the "single converter relaxation method", is proposed and validated. The design procedure of control gains selection using the single converter relaxation method for a multi-converter system is developed. A new method for selecting robust control gains to permit operation over a range of operation conditions is presented. The coordination and interaction of control parameters of multi-terminal VSC are discussed. Using the SCR information at converter bus, the gain scheduling approach to optimal gains is possible. However, compared to robust control gains setting, this approach is more susceptible to system instability.

This thesis presents an investigation into the power transmission limitations imposed on a VSC-HVdc converter by ac system strength and ac system impedance characteristics, quantified by the short circuit ratio (SCR). An important result of this study is that the operation of the converter is not only affected by the SCR’s magnitude, but is also significantly affected by the ac system’s impedance angle at the fundamental frequency. As the ac impedance becomes more resistive, the minimum SCR required at the rectifier side increases from that required for ideally inductive ac impedance, but it decreases at the inverter side. The finite megavolt ampere (MVA) limit of the VSC imposes a further limitation on power transfer, requiring an increase in the value of the minimum SCR. This limitation can be mitigated if additional reactive power support is provided at the point-common-connection. A state-space VSC model was developed and validated with a fully detailed non-linear EMT model. The model showed that gains of the phased-locked-loop (PLL), particularly at low SCRs greatly affect the operation of the VSC-HVdc converter and that operation at low SCRs below about 1.6 is difficult. The model also shows that the theoretically calculated power-voltage stability limit is not attainable in practice, but can be approached if the PLL gains are reduced. The thesis shows that as the VSC-HVdc converter is subject to large signal excitation, a good controller design cannot rely on small signal analysis alone. The thesis therefore proposes the application of optimization tools to coordinate the controls of multiple converters in a dc grid. A new method, the "single converter relaxation method", is proposed and validated. The design procedure of control gains selection using the single converter relaxation method for a multi-converter system is developed. A new method for selecting robust control gains to permit operation over a range of operation conditions is presented. The coordination and interaction of control parameters of multi-terminal VSC are discussed. Using the SCR information at converter bus, the gain scheduling approach to optimal gains is possible. However, compared to robust control gains setting, this approach is more susceptible to system instability.

Indiana University-Purdue University Indianapolis (IUPUI) / This study presents a novel converter configuration that is related to the area DC-DC power converters. To begin with, a brief introduction is given by stating the importance of power electronics. Different types of converters, their operating principles and several new topologies that are being proposed over the years, to suit a particular application with specific advantages are listed in detail. In addition, pro- cedure for performing small signal analysis, which is one among the several averaging techniques is summarized in the first chapter. In the second chapter, small signal modeling is carried out on the single input dual output DC-DC buck converter. This analysis is performed to get a clear un- derstanding on the dynamics of this novel configuration. Routh stability criterion is also applied on this converter topology to determine the limiting conditions for operating the converter in its stability. Third chapter proposes the single input multiple output DC-DC synchronous buck converter. It’s operation, implementation and design are studied in detail. In further, small signal analysis is performed on this topology to determine the transfer function. In the following chapter, results obtained on comparison of a losses between the conventional and traditional topologies are presented in detail. In addition, results achieved during the analysis performed in the previous chapter are displayed. In the end, advantages and its highlights of this novel configuration proposed in this study is summarized. Future course of actions to be done, in bringing this configuration in to practice are discussed as well.

The steady state model and analysis of a phase-shift controlled series resonant inverter (PSC-SRl) is presented. This steady state model includes the evaluation of the zero-voltage switching (ZVS) condition and the determination of the ZVS operating region. Based upon this analysis a frequency control strategy that minimizes circulating energies is proposed. Also, a methodology to design the power stage components, and to predict the duty ratio and the operating frequency range is presented using a PSC-SRl design example operating at 500 kHz and 10 kW. In addition, a novel and simple frequency control circuit that implements the proposed frequency control strategy is provided. Besides, the analysis of the PSC-SRl complete power stage and two control-loop system (frequency control and duty ratio control) is given. Furthermore, the small-signal model and the compensation schemes for each of the control loops is presented. The analytical predictions are compared with experimental data measured from a 500 kHz, 10 kW laboratory prototype and conclusions are drawn. / Ph. D.

Recently, constant-on-time V2 control is more and more popular in industry products due to features of high light load efficiency, simple implementation and fast transient response. In many applications such as cell phone, camera, and other portable devices, low-ESR capacitors such as ceramic caps are preferred due to small size and small output voltage ripple requirement. However, for the converters with ceramic caps, the conventional V2 control suffers from the sub-harmonic oscillation due to the lagging phase of the capacitor voltage ripple relative to the inductor current ripple. Two solutions to eliminate sub-harmonic oscillations are discussed in [39] and the small-signal models are also derived based on time-domain describing function. However, the characteristic of constant-on-time V2 with external ramp is not fully understood and no explicit design guideline for the external ramp is provided. For digital constant on-time V2 control, the high resolution PWM can be eliminated due to constant on-time modulation scheme and direct output voltage feedback [43]. However, the external ramp design is not only related to the amplitude of the limit-cycle oscillation, but also very important to the stability of the system. The previous analysis is not thorough since numerical solution is used. The primary objective of this work is to gain better understanding of the small-signal characteristic for analog and digital constant-on-time V2 with ramp compensations, and provide the design guideline based on the factorized small-signal model. First, constant on-time current-mode control and constant on-time V2 control are reviewed. Generally speaking, constant-on-time current mode control does not have stability issues. However, for constant-on-time V2 control with ceramic caps, sub-harmonic oscillation occurs due to the lagging phase of the capacitor voltage ripple. External ramp compensation and current ramp compensation are two solutions to solve the problem. Previous equivalent circuit model extended by Ray Ridley's sample-and-hold concept is not applicable since it fails to consider the influence of the capacitor voltage ripple. The model proposed in [39] successfully considers the influence from the capacitor voltage ripple by using time-domain describing function method. However, the characteristic of constant-on-time V2 with external ramp is not fully understood. Therefore, more research focusing on the analysis is needed to gain better understanding of the characteristic and provide the design guideline for the ramp compensations. After that, the small-signal model and design of analog constant on-time V2 control is investigated and discussed. The small-signal models are factorized and pole-zero movements are identified. It is found that with increasing the external ramp, two pairs of double poles first move toward each other at half of switching frequency, after meeting at the key point, the two double poles separate, one pair moves to a lower frequency and the other moves to a higher frequency while keeping the quality factor equal to each other. For output impedance, with increasing the external ramp, the low frequency magnitude also increases. The recommended external ramp is around two times the magnitude at the key point K. When Duty cycle is larger, the damping performance is not good with only external ramp compensation, unless very high switching frequency is used. With current ramp compensation, it is recommended to design the current ramp so that the quality factor of the double pole is around 1. With current ramp compensation, the damping can be well controlled regardless of the circuit parameters. Next, the small-signal analysis and design strategy is also extended to digital constant on-time V2 control structure which is proposed in [43]. It is found that the scenario is very similar as analog constant on-time V2 control. The external ramp should be designed around the key point to improve the dynamic performance. The sampling effects of the output voltage require a larger external ramp to stabilize digital constant-on-time V2 control while suffers only a little bit of damping performance. One simple method for measuring control-to-output transfer functions in digital constant-on-time V2 control is presented. The experimental results verify the small-signal analysis except for the high frequency phase difference which reveals the delay effects in the circuit. Load transient experimental results prove the proposed design guideline for digital constant on-time V2 control. As a conclusion, the characteristics of analog and digital constant-on-time V2 control structures are examined and design guidelines are proposed for ramp compensations based on the factorized small-signal model. The analysis and design guideline are verified with simplis simulation and experimental results. / Master of Science