Median filtering is a non-linear filtering technique which is effective in removing impulsive noise from data. In this thesis, directional median filtering has been implemented using cumulative histogram of samples in several directions. Different methods to implement directional median filtering have been proposed. The filtered images are smoothed along the direction of the filtering window. All implementations aimed to generate outputs in the least amount of time, while reducing the resource utilization on hardware. The implementation methods were designed for Xilinx Virtex 5 FPGA devices but were also attempted on Spartan 3E. The proposed methods used less than 30% of the resources on Virtex 5 FPGA but the resource utilization on Spartan 3E exceeded the number of available resources. After an initial delay, methods 1 and 2 generate a new output for every 5 clock cycles while method 3 generates an output for every 1.5 clock cycles.

Title: Obstacle course racing: the effect of obstacles on the total race time during a Spartan Race Objectives: The aim of this study was to determine the effect of 30-burpee punishment on subsequent running speed (SPD), heart rate (HR) following a missed obstacle, and the final race standings during a OCR race. Methods: In our thesis we used a method of analysis in an official Spartan Race in the Czech Republic. 11 male OCR competitors wore a GPS and HR monitor, from which HR and SPD were measured. Three specific obstacles were chosen where nearly all competitors did burpees (spear throw), half did burpees (traverse wall), and nearly none did burpees (monkey bars). The HR and SPD were measured during the entire race, and specifically noted when the competitors arrived at left the obstacle. Results: The average HR of the entire race was 166.45 ± 3.34 beats per minute. The average time spent at the successful obstacles without burpees was 23 ± 17 seconds, while the average time spent at the unsuccessful obstacles with burpees was 124 ± 11 seconds. The change in HR over the course of successful obstacles was 0.79 ± 3.69 beat per minute, while the change in HR during unsuccessful obstacles with burpees was -3.00 ± 6.70 beat per minute. Total time spent at each obstacle correlated with the final...

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The main part of the digital application is its user interface. Users can check the status of the programme or change its state. There are many ways to obtain a suitable interface. During the design stage the simplest interface is chosen that provides the necessary functions. In most cases the interface contains a display. This diploma thesis deals with the design of an extension board to plug in a display to a programmable device, a control algorithm for the display and the design of a simple display interface. There are two ways to design software. The first of them is achieved by the processor PicoBlaze, which contains all the required functions. The second solution is by the state machine written in VHDL language. Both solutions can be used in the same way, but the latter solution is quicker and requires less hardware resources.

This thesis deals with designing and realisation of a bus analyzer. The analyzer is programmed into Spartan-3AN XC3S50AN programmable logic device. The design includes a SRAM parallel memory and a graphical LCD display. Data output is realized through USB, microSD memory card and VGA. The thesis also describes the use of a software microprocessor PicoBlaze for the control of the LCD display and user interface. The last part deals with a test application using an 8-bit microcontroller connected to an alphanumeric display and a discussion over the results.

This masters thesis deals with design of the component facilitating communication between PCI bus and user component. Designed component is simplifying the communication protocol between designed and user components, while advanced functions of PCI bus are preserved. Target platform is COMBO6-PTM card containing FPGA with Spartan 3 technology. Communication with PCI bus is mediated by PLX component. Thesis also contains design of simplified communication protocol.

In this paper, I hope to do a small part to bridge the gap that has emerged in this scholarly debate between the historicist and Straussian views of Spartan society. To that end, this paper will analyze the Spartan Constitution according to the Straussian method. That is, I will engage in a close reading of the text, only referencing outside, secondary sources directly when necessary and appropriate. In other cases, their views will simply color this analysis and be referenced as supporting evidence in footnotes. Strauss chose to have only a superficial interaction with the existing scholarship at the time of publishing his essay, and I therefore believe it will be more beneficial to see what this approach would look like from the historicist perspective. When the same approach is taken, the heart of both camps’ arguments will be exposed, allowing them to be more easily compared. The paper will begin with a reading exploring the themes of Xenophon’s work according to a historicist perspective. After a brief aside explaining and motivating the Straussian esoteric argument to a greater extent, the paper will move on to a similar close-reading of the Spartan Constitution, following Strauss’ essay where appropriate and extending his arguments where necessary. Through this process, the paper aims to show that the perceived separation between the historicist and Straussian interpretations appears to be much greater than it, in reality, is.

The thesis deals with the issue of implementing a PCI interface controller utilizing the FPGA technology. It describes the design and the implementation of a PCI communication card, which is used to control servomotors in cutting machines. In the thesis, the steps taken in designing and implementation of hardware and software parts of the communication card are discussed. The result of the thesis is a functional piece of equipment, which is to be manufactured.

Approved for public release, distribution is unlimited / This thesis will address the planned configuration of Lockheed Martin's Flight Zero, Module Spiral Alpha Littoral Combat Ship (LCS) and the ongoing development of the SPARTAN SCOUT, one of the Navy's Unmanned Surface Vessels (USV). Technology currently available as well as developmental technologies will be recommended for implementation in order to make the LCS and SCOUT assets to Information Operations (IO) objectives. Specific technology will include Outboard, TARBS, HPM, Loudspeakers, LRAD and Air Magnet. This thesis will include an evaluation of the current policy for authorizing Information Operations missions, specifically in the areas of Psychological Operations (PSYOP) and Electronic Warfare (EW). / Lieutenant, United States Navy

Οι συστοιχίες προγραμματιζόμενων πυλών (FPGAs) αποτελούν μια σημαντική τεχνολογία, η οποία επιτρέπει στους σχεδιαστές κυκλωμάτων την παραγωγή συγκεκριμένου σκοπού ολοκληρωμένων κυκλωμάτων σε σύντομο χρόνο. Tα σημαντικότερα των χαρακτηριστικών τους είναι η αρχιτεκτονική τους και η δυνατότητα σχεδιασμού τους μέσω υπολογιστών, η χαμηλή κατανάλωση ισχύος καθώς και το μικρό χρονικό διάστημα που απαιτείται για τον επαναπρογραμματισμό τους. Τα FPGAs είναι κατάλληλα σχεδιασμένα για ψηφιακές εφαρμογές φιλτραρίσματος. Η πυκνότητα των προγραμματιζόμενων αυτών συστημάτων είναι τέτοια ώστε πολύ μεγάλος αριθμός αριθμητικών πράξεων όπως αυτές που προκύπτουν μέσω ψηφιακού φιλτραρίσματος να μπορεί να εφαρμοστεί σε μία μόνο συσκευή. Τα πλεονεκτήματα των FPGA στην υλοποίηση ψηφιακών φίλτρων είναι μεταξύ άλλων οι υψηλότεροι ρυθμοί δειγματοληψίας από παραδοσιακούς DSP chip, το χαμηλότερο κόστος από μια μέτρια ASIC (Application Specific Integrated Circuit, Kύκλωμα οριζόμενο από εφαρμογή) για εφαρμογές μεγάλου όγκου, καθώς και η μεγαλύτερη ευελιξία από όλες τις εναλλακτικές προσεγγίσεις για την υλοποίηση των FIR φίλτρων. Σπουδαιότερο όλων είναι ότι προγραμματίζονται μέσα στο σύστημα και έχουν δυνατότητα επαναπρογραμματισμού για την υλοποίηση διαφόρων εναλλακτικών λειτουργιών φιλτραρίσματος. Στόχος της παρούσας διπλωματικής είναι να συνδυασθούν τεχνικές VLSI και ψηφιακής επεξεργασίας σήματος και μέσω κατανόησης της αρχιτεκτονικής του υπολογιστή να δημιουργηθεί μια χρήσιμη εφαρμογή. Επιλέχθηκε για τον λόγο αυτό: α) η ανάπτυξη ενός FIR φίλτρου σε γλώσσα περιγραφής υλικού, β) υλοποίησή του σε FPGA, γ) εισαγωγή αυτού σε ενσωματωμένο σύστημα και σύνδεση σε διάδρομο δεδομένων επεξεργαστή και δ) έλεγχος του φίλτρου με τη βοήθεια του επεξεργαστή μέσω γλώσσας υψηλού επιπέδου. Η συγγραφή του κώδικα του φίλτρου έγινε σε γλώσσα VHDL, με structural μεθόδους και η προσομοίωση του συστήματος στο Modelsim. Επιπροσθέτως χρησιμοποιήθηκε ο Project Navigator ISE της Xilinx για τον έλεγχο του κώδικα αλλά και τον προγραμματισμό του FPGA Spartan 3E Starter Board. Χρησιμοποιήθηκαν ακόμα τα υποπρογράμματα Plan Ahead και ChipScope Pro του ISE ώστε να ελεγχθεί η λειτουργία του κυκλώματος στο FPGA. To κύκλωμα τελικά εισάγεται σε ενσωματωμένο σύστημα με τη βοήθεια του εργαλείου σχεδίασης EDK της Xilinx και ελέγχεται η λειτουργία του προγραμματίζοντας τον επεξεργαστή Microblaze. Ακόμα ελέγχεται η λειτουργία του φίλτρου για διαφορετικούς συντελεστές FIR φίλτρων που χρησιμοποιούν διαφορετικά παράθυρα και συγκρίνονται οι «ιδανικές» τιμές που παράγονται από το Matlab με αυτές που παράγονται από το φίλτρο. Τέλος μετράται η ενέργεια (δυναμική και στατική) που καταναλώνεται κατά τη λειτουργία του κυκλώματος στο FPGA με τη βοήθεια του XPower Analyzer. / Field-programmable gate arrays (FPGAs) is a technology of great importance that allows the designers to produce specific purpose integrated circuits in a limited amount of time. The most important of their characteristics are their architecture and the ability of their design with the help of computers, the low power dissipation, as well as the need of a short amount of time to be reprogrammed. FPGAs are properly designed for digital filtering applications. The density of these programmable systems is such that a great amount of numerical calculations such as those that result via digital filtering can be applied to one device only. The advantages of FPGAs as for the implementation of digital filters is between others the great rates of sampling compared to traditional DSP chips, their low cost compared to a moderate ASIC (Application Specific Integrated Circuit) for applications that take up a large area, as well as the flexibility compared to alternative approaches for the implementation of FIR filters. Their most important characteristic is that they can be programmed on-chip and that they have the ability of being reprogrammed for the implementation of different filtering purposes. The aim of this thesis is to combine VLSI techniques and digital signal processing techniques and via the understanding of the computer architecture to create a useful application. To fulfill that purpose: a) a FIR filter was designed with the use of a hardware description language b) the filter was implemented by using an FPGA c) the filter was imported to an embedded system and it was connected to the bus of a microprocessor d) the filter was controlled by the microprocessor via a high-level programming language. The filter was designed using the VHDL language, specifically using structural methods, and its simulation was performed with Modelsim. Also the Project Navigator ISE of Xilinx was used to correct unwanted warnings and to program the FPGA Spartan 3E Starter Board. Some other subprograms of ISE were also used, such as Plan Ahead and ChipScope Pro in order to check the performance of the filter. The circuit is finally imported to an embedded system using the Embedded Developer’s Kit (EDK) of Xilinx. Microblaze was the microprocessor that was used to control the filter’s performance. Additionally, the performance of the filter is checked by using different coefficients of FIR filters by different windowing methods. The ideal values that are produced from Matlab are compared to those of the filter. Finally the power dissipation (static and dynamic) of the filter is measured using XPower Analyzer.