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1	Implementation of Directional Median Filtering using Field Programmable Gate Arrays Gundam, Madhuri 17 December 2010 (has links) Median filtering is a non-linear filtering technique which is effective in removing impulsive noise from data. In this thesis, directional median filtering has been implemented using cumulative histogram of samples in several directions. Different methods to implement directional median filtering have been proposed. The filtered images are smoothed along the direction of the filtering window. All implementations aimed to generate outputs in the least amount of time, while reducing the resource utilization on hardware. The implementation methods were designed for Xilinx Virtex 5 FPGA devices but were also attempted on Spartan 3E. The proposed methods used less than 30% of the resources on Virtex 5 FPGA but the resource utilization on Spartan 3E exceeded the number of available resources. After an initial delay, methods 1 and 2 generate a new output for every 5 clock cycles while method 3 generates an output for every 1.5 clock cycles. Histogram Median Sorting Network Directional Median Filtering FPGA CLB LUT Spartan 3E Virtex5
2	Graphical Support for the Design and Evaluation of Configurable Logic Blocks Erxleben, Fredo 15 January 2016 (has links) (PDF) Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given. rekonfigurierbare Schaltkreise Hardwareentwurf Werkzeuge CLB FPGA hardware design reconfigurable hardware tooling ddc:004 rvk:ST 190 rvk:ZN 4950
3	Graphical Support for the Design and Evaluation of Configurable Logic Blocks Erxleben, Fredo 06 May 2015 (has links) Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.:1 Introduction 1.1 Forethoughts 1.2 Theoretical Background 1.2.1 Definitions 1.2.2 Expressing Connections between Circuit Elements 1.2.3 Global Context and Target Function 1.2.4 Problem formulation as QBF and SAT 2 Description of the Implemented Tool 2.1 Design Decisions 2.1.1 Choice of Language, Libraries and Frameworks 2.1.2 Solving the QBF Problem 2.1.3 Design of the Internally Used Meta-Model 2.1.4 User Interface Ergonomics 2.1.5 Aspects of Schematic Visualization 2.1.6 Limitations 2.2 Implemented Features 2.2.1 Basic Interaction 2.2.2 User-Defined Components 2.2.3 Generation of Circuit Symbols 2.2.4 Methods for Specifying Functional Behaviour 3 Implementation Details 3.1 Classes Involved in the Component Meta-Model 3.2 The Document Entry Class and its Factory 3.3 Model and View 3.3.1 The Model Element Hierarchy 3.3.2 The Schematics Element Hierarchy 3.4 The Quantor Interface 4 An Example Workflow 4.1 The Task 4.2 A Component Descriptor for Xilinx’ LUT6-2 4.3 Designing the Model 4.4 Computing the Desired Configuration 5 Summary and Outlook 5.1 Achieved Results 5.2 Suggested Improvements References A Acronyms and Glossary B UML Diagrams info:eu-repo/classification/ddc/004 ddc:004
4	Food webs and phenology models: evaluating the efficacy of ecologically based insect pest management in different agroecosystems Philips, Christopher Robin 02 September 2013 (has links) Integrated pest management (IPM) is defined as an effective and environmentally sensitive approach to pest management that relies on a combination of common-sense practices. Integrated pest management programs use current, comprehensive information on the life cycles of pests and their interactions with host plants and the environment. This information, in combination with available pest control methods, is used to manage pest populations by the most economical means, and with the least possible hazard to people, property, and the environment. True IPM takes advantage of all appropriate pest management options including, as appropriate, the judicious use of pesticides. It is currently estimated the IPM in its full capacity is being practiced on less than ten percent of the agricultural land in the U.S. The primary objective of this research was to evaluate land management decisions and create new tools to promote a true IPM approach and encourage growers to reevaluate their method of insect control. To accomplish this I developed new predictive tools to reduce or eliminate unnecessary insecticide application intended to target cereal leaf beetle in wheat, and assessed a conservation biological control technique, farmscaping, to determine its true impact on lepidopteran pest suppression in collards. / Ph. D. Oulema melanopus cereal leaf beetle CLB small grains wheat IPM integrated pest management degree-days predictive model
5	Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA Iqbal, Rashid January 2006 (has links) <p>This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.</p> Bidirectional motion estimation FPGA Relationally placed macro CLB slice tristate buffers comparator pipelining search upper search lower VHDL Xilinx block matching MeEngine LMC CMC. sum of absolute differences systolic array SARow PE2X8 MeProC 125 MHz Virtex II Pro Electronics Elektronik
6	Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA Iqbal, Rashid January 2006 (has links) This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain. Bidirectional motion estimation FPGA Relationally placed macro CLB slice tristate buffers comparator pipelining search upper search lower VHDL Xilinx block matching MeEngine LMC CMC. sum of absolute differences systolic array SARow PE2X8 MeProC 125 MHz Virtex II Pro Electronics Elektronik
7	FPGA programming with VHDL : A laboratory for the students in the Switching Theory and Digital Design course Azimi, Samaneh, Abba Ali, Safia January 2023 (has links) This thesis aims to create effective and comprehensive learning materials for students enrolled in the Switching Theory and Digital Design course. The lab is designed to enable students to program an FPGA using VHDL in the Quartus programming environment to control traffic intersections with sensors and traffic signals. This laboratory aims to provide students with practical experience in digital engineering design and help them develop the necessary skills to program and implement state machines for regulating traffic environments Engineering and Technology Teknik och teknologier

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