The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will only result from increasing parallelism and introducing asymmetric processing. At the same time, substantial enhancements in the energy efficiency of hardware are required to make use of the increasing transistor density. Unfortunately, the downscaling of transistor size and power will degrade the reliability of the hardware, which must be compensated by software. In this thesis, we present new algorithms and tools that exploit speculative and asymmetric execution to address the performance and reliability challenges of multicore architectures. Our solutions facilitate both the assimilation of software to the changing hardware properties as well as the adjustment of hardware to the software it executes. We use speculation based on transactional memory to improve the synchronization of multi-threaded applications. We show that shared memory synchronization must not only be scalable to large numbers of cores but also robust such that it can guarantee progress in the presence of hardware faults. Therefore, we streamline transactional memory for a better throughput and add fault tolerance mechanisms with a reduced overhead by speculating optimistically on an error-free execution. If hardware faults are present, they can manifest either in a single event upset or crashes and misbehavior of threads. We address the former by applying transactions to checkpoint and replicate the state such that threads can correct and continue their execution. The latter is tackled by extending the synchronization such that it can tolerate crashes and misbehavior of other threads. We improve the efficiency of transactional memory by enabling a lightweight thread that always wins conflicts and significantly reduces the overheads. Further performance gains are possible by exploiting the asymmetric properties of applications. We introduce an asymmetric instrumentation of transactional code paths to enable applications to adapt to the underlying hardware. With explicit frequency control of individual cores, we show how applications can expose their possibly asymmetric computing demand and dynamically adjust the hardware to make a more efficient usage of the available resources.

Database systems have long been optimized to hide the higher latency of storage media, yielding complex persistence mechanisms. With the advent of large DRAM capacities, it became possible to keep a full copy of the data in DRAM. Systems that leverage this possibility, such as main-memory databases, keep two copies of the data in two different formats: one in main memory and the other one in storage. The two copies are kept synchronized using snapshotting and logging. This main-memory-centric architecture yields nearly two orders of magnitude faster analytical processing than traditional, disk-centric ones. The rise of Big Data emphasized the importance of such systems with an ever-increasing need for more main memory. However, DRAM is hitting its scalability limits: It is intrinsically hard to further increase its density. Storage-Class Memory (SCM) is a group of novel memory technologies that promise to alleviate DRAM’s scalability limits. They combine the non-volatility, density, and economic characteristics of storage media with the byte-addressability and a latency close to that of DRAM. Therefore, SCM can serve as persistent main memory, thereby bridging the gap between main memory and storage. In this dissertation, we explore the impact of SCM as persistent main memory on database systems. Assuming a hybrid SCM-DRAM hardware architecture, we propose a novel software architecture for database systems that places primary data in SCM and directly operates on it, eliminating the need for explicit IO. This architecture yields many benefits: First, it obviates the need to reload data from storage to main memory during recovery, as data is discovered and accessed directly in SCM. Second, it allows replacing the traditional logging infrastructure by fine-grained, cheap micro-logging at data-structure level. Third, secondary data can be stored in DRAM and reconstructed during recovery. Fourth, system runtime information can be stored in SCM to improve recovery time. Finally, the system may retain and continue in-flight transactions in case of system failures. However, SCM is no panacea as it raises unprecedented programming challenges. Given its byte-addressability and low latency, processors can access, read, modify, and persist data in SCM using load/store instructions at a CPU cache line granularity. The path from CPU registers to SCM is long and mostly volatile, including store buffers and CPU caches, leaving the programmer with little control over when data is persisted. Therefore, there is a need to enforce the order and durability of SCM writes using persistence primitives, such as cache line flushing instructions. This in turn creates new failure scenarios, such as missing or misplaced persistence primitives. We devise several building blocks to overcome these challenges. First, we identify the programming challenges of SCM and present a sound programming model that solves them. Then, we tackle memory management, as the first required building block to build a database system, by designing a highly scalable SCM allocator, named PAllocator, that fulfills the versatile needs of database systems. Thereafter, we propose the FPTree, a highly scalable hybrid SCM-DRAM persistent B+-Tree that bridges the gap between the performance of transient and persistent B+-Trees. Using these building blocks, we realize our envisioned database architecture in SOFORT, a hybrid SCM-DRAM columnar transactional engine. We propose an SCM-optimized MVCC scheme that eliminates write-ahead logging from the critical path of transactions. Since SCM -resident data is near-instantly available upon recovery, the new recovery bottleneck is rebuilding DRAM-based data. To alleviate this bottleneck, we propose a novel recovery technique that achieves nearly instant responsiveness of the database by accepting queries right after recovering SCM -based data, while rebuilding DRAM -based data in the background. Additionally, SCM brings new failure scenarios that existing testing tools cannot detect. Hence, we propose an online testing framework that is able to automatically simulate power failures and detect missing or misplaced persistence primitives. Finally, our proposed building blocks can serve to build more complex systems, paving the way for future database systems on SCM.

Für den ökonomischen Erfolg konzentrierender Solarkraftwerke und für die Effizienz-steigerung der Industrie durch Weiterverwendung von Abwärme sind skalierbare Hochtemperatur-Wärmespeicher zu vertretbaren Kosten unabdingbar. Bisher sind für dieses Anwendungsgebiet nur sensible Speicher kommerziell verfügbar. Denen gegenüber besitzen chemische Speicher zahlreiche Vorteile. Sie bieten höhere Speicherdichten, geringere Wärmeverluste, die Möglichkeit zur Wärmetransformation durch Variation des Reaktionsdrucks und eine Vielzahl von Reaktionssystemen für eine optimale Prozess-integration. Jedoch befinden sie sich noch in der Entwicklungsphase. Die reversible Gas-/Feststoffreaktion von Calciumoxid und Wasserdampf zu Calcium-hydroxid geschieht bei Temperaturen von 400 – 600 °C und ist damit optimal für solarthermische Anwendungen geeignet. Für die Entwicklung eines Speichers ist neben der thermochemischen Charakterisierung des Speichermaterials ein effizientes, skalierbares Reaktorkonzept nötig. Ein Reaktor mit bewegtem Reaktionsbett ermöglicht die Trennung der zwei charakteristischen Speichergrößen Leistung und Kapazität und stellt damit einen wirtschaftlichen Speicher in Aussicht. Die vorliegende Arbeit befasst sich mit Aufbau und Inbetriebnahme eines neuen Teststandes, in welchem ein innovatives Reaktordesign erprobt werden soll. Sie beschreibt die Auslegung einer planaren Reaktorgeometrie, die einen Schwerkraftfluss des Bettes und die Modularisierung für größere Anlagen gewährleistet. Bei Vorversuchen stellt sich die homo-gene Bewegung des Reaktionsbettes aufgrund dessen Kompressibilität als schwierig heraus. Der angestrebte homogene Massenfluss des Reaktionsmaterials kann durch die ursprünglich eingesetzten Feindosiereinheiten nicht erzielt werden. Sie zeigen sich jedoch für die Temperierung des Speichermediums und die Gasdichtheit des Reaktionsraumes als geeignet. Das homogene Ausfließen wird einer separaten Austragshilfe zugeteilt, welche konstruiert und umgesetzt wird. Experimente mit einem Schaureaktor identifizieren eine Zahnwelle als beste Option. Für einen kommerziellen Speicher wird ein Schlitzschieber empfohlen. Ebenso erfolgen Auslegung und Errichtung der peripheren Anlagenteile, wie z.B. die Fertigung eines Druckhalters zur Steuerung der Reaktionstemperatur. Am Teststand werden somit alle Vorbereitungen abgeschlossen, um Heißversuche bei Reaktionstemperatur durchzuführen.:Kurzfassung.....................................................................II Aufgabenstellung ..............................................................III Inhaltsverzeichnis ..............................................................V Nomenklatur ...................................................................VII Abbildungs- und Tabellenverzeichnis ............................................IX Vorwort ........................................................................XI 1 Einleitung ................................................................... 1 2 Theorie thermischer Energiespeicher .......................................... 3 2.1 Beschreibung von Wärmespeichern ............................................ 3 2.2 Sensible Wärmespeicher ..................................................... 4 2.3 Latente Wärmespeicher....................................................... 9 2.4 Sorptive Wärmespeicher .....................................................12 2.5 Chemische Wärmespeicher ....................................................14 3 Spezifikation des thermochemischen Speichersystems ...........................17 3.1 Thermochemische Grundlagen .................................................17 3.2 Motivation der Aufgabenstellung ............................................20 3.3 Charakterisierung des Reaktionssystems .....................................21 4 Systembeschreibung des Speicherkonzepts ......................................26 4.1 Kurzdarstellung der Ausgangssituation ......................................26 4.2 Weiterentwicklung zum bewegten Reaktionsbett ...............................27 4.2.1 Theorie des bewegten Reaktionsbettes .....................................27 4.2.2 Konstruktion des Reaktors ................................................28 4.2.3 Förderung des Speichermaterials ..........................................31 4.3 Periphere Anlagenteile .....................................................33 4.3.1 Anlagenschema ............................................................33 4.3.2 Entwurf des Druckhalters .................................................35 INHALTSVERZEICHNIS VI 4.3.3 Ausführung der Elektro- und Messtechnik ..................................37 5 Experimentelle Untersuchungen ................................................39 5.1 Versuchsdurchführung .......................................................39 5.2 Betrieb der Fördereinheiten ................................................40 5.3 Optimierung der Fördereinheiten ............................................44 5.3.1 Inaktive Mischpaddel .....................................................44 5.3.2 Modifizierte Mischpaddel .................................................47 5.4 Erkenntnisse ...............................................................49 6 Finales Konzept des Versuchsstandes ..........................................50 6.1 Lösungsansätze für den Massenfluss .........................................50 6.2 Gestaltung der Austragshilfe ...............................................54 7 Zusammenfassung und Ausblick .................................................57 Eidesstattliche Erklärung ......................................................59 Literatur- und Quellenverzeichnis ..............................................60 Anlagen ........................................................................63 A.1. Parametrierung des Temperaturwächters (Kapitel 4.3.3) .....................63 A.2. Inhalt des beigelegten Datenträgers (Einband) .............................63 A.3. Berechnung der Aufheizstrecke des Stickstoffstroms (Kapitel 4.3.1) ........64 A.4. Konstruktionszeichnung des Druckhalters (Kapitel 4.3.2) ...................65 A.5. Dampftafel: Sättigungsdampfdruck von Wasserdampf (Kapitel 4.3.2) ..........66 A.6. Stromlaufpläne und Baugruppenliste des Teststandes (Kapitel 4.3.3) ... ....67 A.7. Ermittlung der Kabelquerschnitte für Stromlaufplan (Kapitel 4.3.3) ........73 A.8. Parametrierung der Frequenzumrichter (Kapitel 5.1) ....................... 74 A.9. Ergebnisse der Kalibiermessungen (Kapitel 5.2) ............................75 A.10. Berechnungen zur Dynamik des Schlitzschiebers (Kapitel 6.1) ............. 76 A.11. Konstruktionszeichnungen der Austragshilfe (Kapitel 6.2) .................77

Ferroelectrics are theoretically an ideal solution for low write power nonvolatile memories. However, the complexity of ferroelectric perovskites has hindered the scaling of such devices to competitive feature sizes. The discovery of ferroelectricity in hafnium oxide solved this issue. Ferroelectric memories in three variants, capacitor based ferroelectric RAM, ferroelectric field effect transistors and ferroelectric tunneling junctions have become competitors for future memory solutions again. In this paper, the basics and current status of hafnium oxide based ferroelectric memory devices is described and recent results are shown.

GPUs are increasingly adopted for large-scale database processing, where data accesses represent the major part of the computation. If the data accesses are irregular, like hash table accesses or random sampling, the GPU performance can suffer. Especially when scaling such accesses beyond 2GB of data, a performance decrease of an order of magnitude is encountered. This paper analyzes the source of the slowdown through extensive micro-benchmarking, attributing the root cause to the Translation Lookaside Buffer (TLB). Using the micro-benchmarks, the TLB hierarchy and structure are fully analyzed on two different GPU architectures, identifying never-before-published TLB sizes that can be used for efficient large-scale application tuning. Based on the gained knowledge, we propose a TLB-conscious approach to mitigate the slowdown for algorithms with irregular memory access. The proposed approach is applied to two fundamental database operations - random sampling and hash-based grouping - showing that the slowdown can be dramatically reduced, and resulting in a performance increase of up to 13×.

In this thesis, we investigate weighted tree automata with storage theoretically. This model generalises finite state automata in three dimensions: (i) from words to trees, (ii) by using an arbitrary storage type in addition to a finite-state control, and (iii) by considering languages in a quantitative setting using a weight structure.

The ferroelectricity in fluorite structure based hafnium oxide (HfO2) material expanded the horizon for realizing nonvolatile ferroelectric memory concepts. Due to the excellent HfO2 ferroelectric film properties, CMOS compatibility, and scalability; the material is foreseen as a replacement of the lead based ferroelectric materials with a big game changing potential for the emerging ferroelectric memories. In this thesis, the development of novel memory concepts based on the ferroelectric or antiferroelectric HfO2 material is reported. The ferroelectric field effect transistor (FeFET) memory concept offers a low power, high-speed, nonvolatile, and one cell memory solution ideal for embedded memory realization. As an emerging concept based on a novel ferroelectric material, the FeFET is challenged with key performance aspects intrinsic to the underlying physics of the device. A central part of this thesis is the development of FeFET through material and gate stack engineering, in turn leading to innovative novel device concepts. The conceptual innovation, process development, and electrical assessment are explored for an ferroelectric or antiferroelectric HfO2 based nonvolatile memories with focus on the underlying device physics. The impact of the ferroelectric material on the FeFET physics is explored via the screening of different HfO2 based ferroelectric materials, thicknesses, and the film doping concentration. The impact of material interfaces and substrate doping conditions are explored on the stack engineering level to achieve a low power and reliable FeFET. The material optimization leads to the concept of ferroelectric lamination, i.e. a dielectric interlayer between multi ferroelectric ones, to achieve a novel multilevel data storage in FeFET at reduced device variability. Toward a low power FeFET, the stack structure tuning and dual ferroelectric layer integration are explored through an MFM and MFIS integration in a single novel FeFET stack. The charge trapping effect during the FeFET switching captures the dynamics of the hysteresis polarization switching inside the stack with direct impact on the interfacial layer field. Even though manifesting as a clear drawback in FeFET operation, it can be utilized in Flash, leading to a novel hybrid low power and high-speed antiferroelectric based charge trap concept. Furthermore, the FeFET reliability is studied covering the role of operating temperature and the ferroelectric wakeup phenomenon observed in the FeFET. The temperature modulated operation, role of the high-temperature pyroelectric effect, and the temperature induced endurance and retention reliability are studied.:Table of Contents Abstract Table of Contents 1. Introduction 2. Fundamentals 2.1. Basics of Ferroelectricity 2.2. The FeFET Operation Principle and Gate Stack Theory 2.3. Structure and Outline of the PhD Thesis 3. The Emerging Memory Optimization Cycle: From Conceptual Design to Fabrication 3.1. The FeFET Conceptual Design and Layout Implementation 3.2. Gate First FeFET Fabrication: Material and Gate Stack Optimization 3.3. Novel Gate First based Memory Concepts: Device Integration and Stack Optimization 3.4. Device Characterization: Electrical Testing Schemes 4. The Emerging FeFET Memory: Material and Gate Stack Optimization 4.1. Material Aspect of FeFET Optimization: Role of the FE Material Properties 4.2. The Stack Aspect of FeFET Optimization: Role of the Interface Layer Properties 4.3. The Stack Aspect of FeFET Optimization: Role of the Substrate Implant Doping 4.4. Summary 5. A Novel Multilevel Cell FeFET Memory: Laminated HSO and HZO Ferroelectrics 5.1. The Laminate MFM and Stack Characteristics 5.2. The Laminate based FeFET Memory Switching 5.3. The Laminate FeFET Multilevel Coding Operation (1 bit, 2 bit, 3 bit/cell) 5.4. The Maximum Laminate FeFET MW Dependence on FE Stack Thickness 5.5. The Role of Wakeup and Charge Trapping 5.6. The Laminate MLC FeFET Area Dependence 5.7. The Laminate MLC Retention and Endurance 5.8. Impact of Pass Voltage Disturb on Laminate based NAND Array Operation 5.9. The Laminate FeFET based Synaptic Device 5.10. Summary 6. A Novel Ferroelectric MFMFIS FeFET: Toward Low Power and High-Speed NVM 6.1. The MFMFIS FeFET P-E and FET Characteristics 6.2. The MFMFIS based Memory Characteristics 6.3. The Impact of MFMFIS Stack Structure Tuning 6.4. The Maximum MFMFIS FeFET Memory Window 6.5. The Role of Device Scalability and Variability 6.6. The MFMFIS Area Tuning for Low Power Operation 6.7. The MFMFIS based FeFET Reliability 6.8. The Synaptic MFMFIS based FeFET 6.9. Summary 7. A Novel Hybrid Low Power and High-Speed Antiferroelectric Boosted Charge Trap Memory 7.1. The Hybrid Charge Trap Memory Switching Characteristics 7.2. The Role of Polarization Switching on Optimal Write Conditions 7.3. The Impact of FE/AFE Properties on the Charge Trap Maximum Memory Window 7.4. The Hybrid AFE Charge Trap Multi-level Coding and Array Operation 7.5. The Global Variability and Area Dependence of the Charge Trap Memory Window 7.6. The AFE Charge Trap Reliability 7.7. The Hybrid AFE Charge Trap based Synapse 7.8. Summary 8. The Emerging FeFET Reliability: Role of Operating Temperature and Wakeup Effect 8.1. The FeFET Temperature Reliability: A Temperature Modulated Operation 8.2. The FeFET Temperature Reliability: Role of the Pyroelectric Effect 8.3. The FeFET Temperature Reliability: Endurance and Retention 8.4. The Impact of Ferroelectric Wakeup on the FeFET Memory Reliability 8.5. Summary 9. Closure: What this Thesis has Solved? 9.1. How material selection/development influence the FeFET? 9.2. Why the FeFET Still Operates at High Write Conditions? 9.3. Why the FeFET Endurance is still a Challenge? 9.4. Can the FeFET become Multi-bit Storage Memory? 9.5. How the Scalability Determine FeFET Chances? 10. Summary 11. Bibliography List of symbols and abbreviations List of Publications Acknowledgment Erklärung

We report on the retention properties of double-layer hafnium zirconium oxide (Hf₀.₅Zr₀.₅O₂; HZO) based ferroelectric tunnel junctions (FTJ). Utilizing HZO as the ferroelectric layer and aluminum oxide (Al₂ O₃) as the tunneling barrier a scalable FTJ memory operation with good endurance and an on/off ratio of about 10 was achieved. Due to inherent depolarization fields from the double layer structure, the device suffers from strong retention loss over time. An extrapolation to 10 years at room temperature shows vanishing differences between the on and off state currents. We propose a way to avert this retention loss by using a constant bias that can be built-in by a work function difference from the metal electrode. This leads to more stable on-current retention and only small off-current increase, giving rise to an improved retention behavior of the FTJ.

The work investigates the selective deposition of cobalt oxide via atomic layer deposition. Methoxysilanes chlorosilane and poly(trimethylsilylstyrene) self-assembled monolayers are utilized to prevent wetting of water and cobalt bis(N-tert butyl, N'-ethylpropionamidinate) from the substrate, thereby controlling nucleation on the substrate and providing a pathway to enable selective deposition of cobalt oxide. Sr and Al are deposited atop the oxide films to scavenge oxygen and yield carbon-free cobalt metal films. Thermal reduction of the oxide layer in the presence of CO and H 2 was also investigated as an alternative. Finally, we demonstrate control over the tunability of the coercivity of the resultant films by controlling the reduction conditions.

In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert. / In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.