The characteristics of irregular algorithms make a parallel implementation difficult, especially for PC clusters or clusters of SMPs. These characteristics may include an unpredictable access behavior to dynamically changing data structures or strong irregular coupling of computations. Problems are an unknown load distribution and expensive irregular communication patterns for data accesses and redistributions. Thus the parallel implementation of irregular algorithms on distributed memory machines and clusters requires a special organizational mechanism for a dynamic load balance while keeping the communication and administration overhead low. We propose task pool teams for implementing irregular algorithms on clusters of PCs or SMPs. A task pool team combines multithreaded programming using task pools on single nodes with explicit message passing between different nodes. The dynamic load balance mechanism of task pools is generalized to a dynamic load balance scheme for all distributed nodes. We have implemented and compared several versions for task pool teams. As application example, we use the hierarchical radiosity algorithm, which is based on dynamically growing quadtree data structures annotated by varying interaction lists expressing the irregular coupling between the quadtrees. Experiments are performed on a PC cluster and a cluster of SMPs.

Berechnung, Auslegung, Konstruktion und Wirtschaftlichkeitsbetrachtungen zu einem Kies-Luft-Speicher. Verbesserung der Raumklimatisierung eines 100m² großen Gebäudes in Syrien.

Non-volatile memory technologies (NVM) introduce a novel class of devices that combine characteristics of both storage and main memory. Like storage, NVM is not only persistent, but also denser and cheaper than DRAM. Like DRAM, NVM is byte-addressable and has lower access latency. In recent years, NVM has gained a lot of attention both in academia and in the data management industry, with views ranging from skepticism to over excitement. Some critics claim that NVM is not cheap enough to replace flash-based SSDs nor is it fast enough to replace DRAM, while others see it simply as a storage device. Supporters of NVM have observed that its low latency and byte-addressability requires radical changes and a complete rewrite of storage management architectures. This thesis takes a moderate stance between these two views. We consider that, while NVM might not replace flash-based SSD or DRAM in the near future, it has the potential to reduce the gap between them. Furthermore, treating NVM as a regular storage media does not fully leverage its byte-addressability and low latency. On the other hand, completely redesigning systems to be NVM-centric is impractical. Proposals that attempt to leverage NVM to simplify storage management result in completely new architectures that face the same challenges that are already well-understood and addressed by the traditional architectures. Therefore, we take three common storage management architectures as a starting point, and propose incremental changes to enable them to better leverage NVM. First, in the context of log-structured merge-trees, we investigate the impact of storing data in NVM, and devise methods to enable small granularity accesses and NVM-aware caching policies. Second, in the context of B+Trees, we propose to extend the buffer pool and describe a technique based on the concept of optimistic consistency to handle corrupted pages in NVM. Third, we employ NVM to enable larger capacity and reduced costs in a index+log key-value store, and combine it with other techniques to build a system that achieves low tail latency. This thesis aims to describe and evaluate these techniques in order to enable storage management architectures to leverage NVM and achieve increased performance and lower costs, without major architectural changes.:1 Introduction 1.1 Non-Volatile Memory 1.2 Challenges 1.3 Non-Volatile Memory & Database Systems 1.4 Contributions and Outline 2 Background 2.1 Non-Volatile Memory 2.1.1 Types of NVM 2.1.2 Access Modes 2.1.3 Byte-addressability and Persistency 2.1.4 Performance 2.2 Related Work 2.3 Case Study: Persistent Tree Structures 2.3.1 Persistent Trees 2.3.2 Evaluation 3 Log-Structured Merge-Trees 3.1 LSM and NVM 3.2 LSM Architecture 3.2.1 LevelDB 3.3 Persistent Memory Environment 3.4 2Q Cache Policy for NVM 3.5 Evaluation 3.5.1 Write Performance 3.5.2 Read Performance 3.5.3 Mixed Workloads 3.6 Additional Case Study: RocksDB 3.6.1 Evaluation 4 B+Trees 4.1 B+Tree and NVM 4.1.1 Category #1: Buffer Extension 4.1.2 Category #2: DRAM Buffered Access 4.1.3 Category #3: Persistent Trees 4.2 Persistent Buffer Pool with Optimistic Consistency 4.2.1 Architecture and Assumptions 4.2.2 Embracing Corruption 4.3 Detecting Corruption 4.3.1 Embracing Corruption 4.4 Repairing Corruptions 4.5 Performance Evaluation and Expectations 4.5.1 Checksums Overhead 4.5.2 Runtime and Recovery 4.6 Discussion 5 Index+Log Key-Value Stores 5.1 The Case for Tail Latency 5.2 Goals and Overview 5.3 Execution Model 5.3.1 Reactive Systems and Actor Model 5.3.2 Message-Passing Communication 5.3.3 Cooperative Multitasking 5.4 Log-Structured Storage 5.5 Networking 5.6 Implementation Details 5.6.1 NVM Allocation on RStore 5.6.2 Log-Structured Storage and Indexing 5.6.3 Garbage Collection 5.6.4 Logging and Recovery 5.7 Systems Operations 5.8 Evaluation 5.8.1 Methodology 5.8.2 Environment 5.8.3 Other Systems 5.8.4 Throughput Scalability 5.8.5 Tail Latency 5.8.6 Scans 5.8.7 Memory Consumption 5.9 Related Work 6 Conclusion Bibliography A PiBench

The polarization reversal in ferroelectric HfO₂ is adopted to store information in three distinct device classes - ferroelectric field effect transistors (FeFET), ferroelectric capacitors (FeCAP) and ferroelectric tunnel junctions (FTJ). Common to all three concepts is the adoption of a ferroelectric layer stack that acts either as gate dielectric in the FeFET or as the capacitor dielectric and tunneling barrier in the FeCAP or FTJ, respectively. A composite structure including an inevitably or purposefully formed dielectric layer is frequently adopted. In this work we report on the co-existence of all three memory concepts within one device structure and propose a 2T1C ferroelectric memory cell that allows the operation and comparative characterization of the trinity of ferroelectric memory devices.

Exploiting thread-level parallelism has become a part of mainstream programming in recent years. Many approaches to parallelization require threads executing in parallel to also synchronize occassionally (i.e., coordinate concurrent accesses to shared state). Transactional Memory (TM) is a programming abstraction that provides the concept of database transactions in the context of programming languages such as C/C++. This allows programmers to only declare which pieces of a program synchronize without requiring them to actually implement synchronization and tune its performance, which in turn makes TM typically easier to use than other abstractions such as locks. I have investigated and implemented the building blocks that are required for a high-performance, practical, and realistic TM. They host several novel algorithms and optimizations for TM implementations, both for current hardware and future hardware extensions for TM, and are being used in or have influenced commercial TM implementations such as the TM support in GCC.

Algae provide an important role in aquatic food web and biochemical cycles in aquatic systems. They are affected by different environmental factors, such as pH, light, temperature and nutrients. This study aimed to describe the composition abundance and density of phytoplankton in the Hoa Binh reservoir during period from March to December 2011. Phytoplankton samples were collected monthly at four sampling stations. Result obtained showed that 6 phytoplankton classes were recorded: Cyanobacteria, Chlorophyceae, Bacillariophyceae, Euglenophyceae, Dinophyceae and Cryptophyceae. Bacillariophyceae and Cyanobacteria were the most abundant phytoplankton families constituting 61% and 32% respectively of total phytoplankton community. Colony-forming and solitary filamentous-forming of Cyanobacteria group (e.g. Microcystis aeruginosa, M. wesenbergi and Oscillatoria sp. respectively) were a common component of phytoplankton community in the early summer and autumn periods (April and September). The total cell densities of phytoplankton varied seasonally from 84210 to 100x106 cell/L. Phytoplankton density varied with season with high values in early summer and winter (April and December) and low values in summer – autumn periods (from June to October). / Tảo đóng vai trò quan trọng trong mạng lưới thức ăn và chu trình sinh địa hóa của thủy vực và chúng chịu sự chi phối của nhiều yếu tố môi trường như ánh sáng, pH, nhiệt độ và dinh dưỡng. Nghiên cứu này trình bày đa dạng thành phần loài và biến động sinh khối thực vật phù du tại hồ chứa Hòa Bình từ tháng 3 đến tháng 12 năm 2011. Các mẫu thực vật nổi được thu thập hàng tháng tại 4 điểm. Kết quả đã xác định được 6 lớp tảo chính bao gồm: Vi khuẩn lam, tảo lục, tảo silic, tảo mắt, tảo giáp và tảo lông roi hai rãnh. Nhóm tảo silic và Vi khuẩn lam chiếm ưu thế với độ phong phú tương đối là 61% và 32% tương ứng trong quần xã thực vật nổi. Vi khuẩn lam dạng tập đoàn và dạng sợi (Microcystis aeruginosa, M. wesenberg, Oscillatoria sp. tương ứng) chiếm ưu thế trong quần xã thực vật nổi vào các thời điểm đầu hè và mùa thu (tháng 4 và tháng 9). Tổng mật độ tế bào thực vật nổi dao động từ 84210 đến 100 x106 cell/L. Mật độ thực vật nổi biển động theo mùa với sinh khối tê bào cao vào đầu hè và mùa đông (tháng 4 và tháng 12) và sinh khối tế bào thấp vào các mùa hè và thu (tháng 6 đến tháng 10).

Storage Class Memory (SCM) is a novel class of memory technologies that promise to revolutionize database architectures. SCM is byte-addressable and exhibits latencies similar to those of DRAM, while being non-volatile. Hence, SCM could replace both main memory and storage, enabling a novel single-level database architecture without the traditional I/O bottleneck. Fail-safe persistent SCM allocation can be considered conditio sine qua non for enabling this novel architecture paradigm for database management systems. In this paper we present PAllocator, a fail-safe persistent SCM allocator whose design emphasizes high concurrency and capacity scalability. Contrary to previous works, PAllocator thoroughly addresses the important challenge of persistent memory fragmentation by implementing an efficient defragmentation algorithm. We show that PAllocator outperforms state-of-the-art persistent allocators by up to one order of magnitude, both in operation throughput and recovery time, and enables up to 2.39x higher operation throughput on a persistent B-Tree.

In dieser Arbeit sind Dielektrika mit hoher relativer Permittivität untersucht worden, welche eine Anwendung in dynamischen Halbleiter-Speicherzellen (DRAM) zum Ziel haben. Sie unterstützen das Weiterführen der fortschreitenden Miniaturisierung der Speicherzellen bzw. der Erhöhung der Speicherdichten und dienen als Alternative zu den bisherigen Standardmaterialien SiO2 und Si3N4. Als Herstellungsmethoden für mehrkomponentige Oxide wurden zum einen die Molekularstrahl-Deposition und zum anderen die Ko-Sputterdeposition gewählt, da sie eine sehr große Flexibilität bei der Wahl der abscheidbaren Elemente und Oxide bieten sowie eine hohe Ratenstabilität und Reinheit versprechen. Hierfür wurden Prozesse zur simultanen Abscheidung dünner Schichten aus mehreren Quellen entwickelt und optimiert. Als neuartige Dielektrika wurden ZrO2 und SrZrO3 hergestellt und untersucht. Hierbei wurden besonders die dielektrischen und kristallographischen Eigenschaften in Abhängigkeit von der Stöchiometrie umfangreich analysiert. Die maximale erreichte Dielektrizitäszahl des ZrO2 betrug ca. 30 und die des SrZrO3 ca. 31. Es wurde dargelegt, dass die Dielektrizitätszahl des ZrO2 unter bestimmten Umständen von der Schichtdicke im Bereich von 5 bis 50 nm abhängig ist. Dies konnte durch die Beimischung von Sr erfolgreich stabilisiert werden. Die für DRAM-Anwendungen zum Teil zu hohen Leckstromdichten konnten durch die Entwicklung eines neuen Ausheilverfahrens deutlich verbessert werden. Aufgrund der hohen Dielektrizitätszahl in Verbindung mit gesenkten Leckströmen konnte für ZrO2 eine minimale kapazitätsäquivalente Dicke von CET = 1,2 nm und für SrZrO3 eine CET = 1,4 nm erreicht werden, welche der DRAM-Grenze für Leckstromdichten von J = 100 nA/cm² genügen. Diese Werte sind deutlich geringer als die dünnsten, theoretisch möglichen Schichten des klassischen SiO2 und Si3N4, wodurch sowohl ZrO2 als auch SrZrO3 ihr Potential, als Alternative für Speicheranwendungen zu dienen, unterstreichen. / In this work, dielectrics with a high relative permittivity were investigated, which are intended for the application in dynamic random access memory cells (DRAM). Their successful implementation ensures the continuation of the ongoing scaling of memory devices, thus increasing the storage density. They serve as alternative for the standard materials SiO2 and Si3N4. In order to to grow multi-component oxides, molecular beam deposition as well as co-sputter deposition were chosen, given their high flexibility to evaporate various elements and oxides. Additionally, both hold their promise of a good control of the growth rate and high purity. Therefore processes were developed and optimized for growing thin films by using multiple sources simultaneously. The alternative dielectrics ZrO2 and SrZrO3 were fabricated and analysed. Especially, the dependency of the dielectric and crystallographic properties on the stoichiometry were evaluated comprehensively. The highest achieved relative permittivity for ZrO2 and SrZrO3 were approx. 30 and 31, respectively. Under specific and controllable circumstances, the relative permittivity of ZrO2 was found to depend on the film thickness in the range of 5 to 50 nm. However, the admixture of Sr stabilises the relative permittivity. In some cases, the leakage current densities of ZrO2 and SrZrO3 films were too high for DRAM applications. It was possible to decrease those currents drastically by developing a new healing process. The high permittivity in addition with the improved leakage current densities led in the case of ZrO2 to a minimum capacitance equivalent thickness of CET = 1.2 nm and in the case of SrZrO3 to a CET = 1.4 nm, which fulfill the DRAM leakage current density limit of J = 100 nA/cm². Those values are much lower than the thinnest theoretically possible films of the conventional SiO2 or Si3N4. Therefore, ZrO2 and SrZrO3 accentuate their potential for memory applications.

In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert. / In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.

Die "Mitteilungen des URZ" informieren die Nutzer des Universitätsrechenzentrums der TU Chemnitz umfassend über neue Dienste und Projekte, vermitteln ggf. Hintergrundwissen und dienen der Berichterstattung.