The path of steepest ascent can used to optimize a response in an experiment, but problems can occur with multiple responses. Past approaches to this issue such as Del Castillo’s overlap of confidence cones and Mee and Xiao’s Pareto Optimality, have not considered the correlations of the responses or parameter uncertainty. We propose a new method using the Bayesian reliability to calculate this direction. We utilize this method with four examples: a 2 factor, 2-response experiment where the paths of steepest ascent are similar, ensuring our results match Del Castillo’s and Mee and Xiao’s; a 2 factor, 2-response experiment with disparate paths of steepest ascent illustrating the importance of the Bayesian reliability; two simulation examples, showing parameter uncertainty is considered; and a 5 factor, 2-response experiment proving this method is not dimensional limited. With a Bayesian reliable point, a direction in multivariate steepest ascent can be found.

Accurate transistor models are important in wireless and microwave circuit design. Large-signal field-effect transistor (FET) models are generally extracted from current-voltage (IV) characteristics, small-signal S-parameters, and large-signal measurements. This dissertation describes improved characterization and measurement validation techniques for FET models that correctly account for thermal and trapping effects. Demonstration of a customized pulsed-bias, pulsed-RF S-parameter system constructed by the author using a traditional vector network analyzer is presented, along with the design of special bias tees to allow pulsing of the bias voltages. Pulsed IV and pulsed-bias S-parameter measurements can provide results that are electrodynamically accurate; that is, thermal and trapping effects in the measurements are similar to those of radio-frequency or microwave operation at a desired quiescent bias point. The custom pulsed S-parameter system is benchmarked using passive devices and advantages and tradeoffs of pulsed S-parameter measurements are explored. Pulsed- and continuous-bias measurement results for a high-power transistor are used to validate thermal S-parameter correction procedures. A new implementation of the steepest-ascent search algorithm for load-pull is presented. This algorithm provides for high-resolution determination of the maximum power and associated load impedance using a small number of measured or simulated reflection-coefficient states. To perform a more thorough nonlinear model validation, it is often desired to find the impedance providing maximum output power or efficiency over variations of a parameter such as drain voltage, input power, or process variation. The new algorithm enables this type of validation that is otherwise extremely tedious or impractical with traditional load-pull. A modified nonlinear FET model is presented in this work that allows characterization of both thermal and trapping effects. New parameters and equation terms providing a trapping-related quiescent-bias dependence have been added to a popular nonlinear ("Angelov") model. A systematic method for fitting the quiescent-dependence parameters, temperature coefficients, and thermal resistance is presented, using a GaN high electron-mobility transistor as an example. The thermal resistance providing a good fit in the modeling procedure is shown to correspond well with infrared measurement results.