Widespread adoption of phased array technologies has been hindered primarily by the high cost associated Transmitter/Receiver (T/R) modules. In conventional phased arrays, these vital elements often comprise up to fifty-percent of the entire array's expense. Recent development of a new type of phased array - the Electronically Steerable Passive Array Radiator (ESPAR) - is underway at laboratories around the globe. This innovative concept utilizes mutual coupling to excite neighboring (passive) elements placed in the near field of a center-driven (active) radiator. Using this method, T/R modules are only required for the active radiators. The radiation pattern of an ESP AR is controlled electronically by means of variable reactive loading of the passive antenna elements. In order to attain the full range of beam steering offered by this array, a broad range of reactance is required at the input port of each passive antenna. This thesis presents a varactor-based reactive network design that can accurately and reliably produce a wide range of reactance. The purpose of this research was to design a network compatible with the requirements of the ESP AR phased array, which is in development at the Antennas, RF, and Microwave Integrated Systems CARMI) laboratory at the University of Central Florida. To this end, an elaborate survey weighing different varactor-based reactive network and DC bias tee designs was conducted. This study took into account the practical issues and limiting factors that arose during design and implementation of such a network. While this specific network design was constrained to operate at 3 GHz, the proposed design methodology may be applied to realize reactive networks at other frequencies. This flexibility allows incorporation into similar ESPAR's and a plethora of other relevant devices.

Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given. / <p>QC 20140114</p>

Accurate transistor models are important in wireless and microwave circuit design. Large-signal field-effect transistor (FET) models are generally extracted from current-voltage (IV) characteristics, small-signal S-parameters, and large-signal measurements. This dissertation describes improved characterization and measurement validation techniques for FET models that correctly account for thermal and trapping effects. Demonstration of a customized pulsed-bias, pulsed-RF S-parameter system constructed by the author using a traditional vector network analyzer is presented, along with the design of special bias tees to allow pulsing of the bias voltages. Pulsed IV and pulsed-bias S-parameter measurements can provide results that are electrodynamically accurate; that is, thermal and trapping effects in the measurements are similar to those of radio-frequency or microwave operation at a desired quiescent bias point. The custom pulsed S-parameter system is benchmarked using passive devices and advantages and tradeoffs of pulsed S-parameter measurements are explored. Pulsed- and continuous-bias measurement results for a high-power transistor are used to validate thermal S-parameter correction procedures. A new implementation of the steepest-ascent search algorithm for load-pull is presented. This algorithm provides for high-resolution determination of the maximum power and associated load impedance using a small number of measured or simulated reflection-coefficient states. To perform a more thorough nonlinear model validation, it is often desired to find the impedance providing maximum output power or efficiency over variations of a parameter such as drain voltage, input power, or process variation. The new algorithm enables this type of validation that is otherwise extremely tedious or impractical with traditional load-pull. A modified nonlinear FET model is presented in this work that allows characterization of both thermal and trapping effects. New parameters and equation terms providing a trapping-related quiescent-bias dependence have been added to a popular nonlinear ("Angelov") model. A systematic method for fitting the quiescent-dependence parameters, temperature coefficients, and thermal resistance is presented, using a GaN high electron-mobility transistor as an example. The thermal resistance providing a good fit in the modeling procedure is shown to correspond well with infrared measurement results.

Due to the current research needs and the lack of commercial multi-channel, multi-constellation GNSS receivers, a two-board solution has been developed so it can be mated with and take advantage of the processing power of the FPGA board branded as MicroZed. In order to achieve the proposed goals, an initial phase for assessing and updating the older design, building, and testing of SiGe modules (including both the electronics and casings) has been carried out. The results included demonstrate performances at logging GPS-L1 data with similar C/N0 and AGC values as the previous versions of the modules and offering navigation solutions with accuracies of a few meters. Secondly, a first iteration and design proposal for the new generation receiver has been proposed for GPS and GLONASS L1 and L2, which has been manufactured and tested. Partial tests have been performed due to the flaws of the current revision of the MicroZed Board in regards to its communication peripherals, and the results have validated the receiver’s design provided certain modifications are considered for future iterations. Furthermore, voltage and frequency tests have provided results with an error of less than 7%, and signal tests have provided C/N0 values similar to those of the SiGe modules of around 47[dB-Hz] which will be a useful baseline for future iterations. Finally, a design proposal for an Interface Board used between the older NT1065_PMOD Board and other FPGA boards carrying the standardized FMC connectors has been added to the report and negotiations with manufacturers have been engaged.