Global ETD Search

1	Měřicí systém termoluminiscence / Thermoluminescence measurement system Matějka, Tomáš January 2018 (has links) This thesis deals with revision and design of electronic for measuring system PSI TL 500 which is designed for measurement of thermoluminescence phenomena in photosystem II. Thesis describes principles and properties of the measuring system in its current form and changes for the new version are discussed. Digital control part based on Xilinx Zynq platform is designed. Revision of analog measuring part of system is made and partial changes are implemented.
2	Kamera pro aplikace v biologii / Camera for biological applications Jurák, Petr January 2017 (has links) This diploma thesis is focused on the design of IP blocks for thermal camera. This termal camera is intended for plant research. The main part of the thermal camera is an infrared detector that detects a frequency in the range of 8 – 14 m. The analogue signal obtained is modified and subsequently digitized. The detector also includes a Peltier device which is designed for both detector cooling and heating, and is controlled by an external signal. The MicroZed development board implements IP blocks. The thermal camera is designed to be controlled from the MicroZed board. Device analysis is first described from the theoretical part to the design of IP blocks.
3	Vývoj RGB kamery s vysokým rozlišením / Development of high resolution RGB camera Madeja, Jiří January 2017 (has links) Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.
4	High-Speed Programmable FPGA Configuration Memory Access Using JTAG Gruwell, Ammon Bradley 01 April 2017 (has links) Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications. FPGA JTAG scrubbing fault injection radiation testing laser testing C++ Python BYU configuration readback reliability SEU Xilinx bitstream upset mitigation hardware software high speed configuration memory CRAM SRAM Joint Test Action Group ionizing radiation space aerospace interface serial ARM processor architecture programmable logic MicroZed Zynq Linux Electrical and Computer Engineering
5	New Generation 4-Channel GNSS Receiver : Design, Production, and Testing Antoja Lleonart, Guillem January 2018 (has links) Due to the current research needs and the lack of commercial multi-channel, multi-constellation GNSS receivers, a two-board solution has been developed so it can be mated with and take advantage of the processing power of the FPGA board branded as MicroZed. In order to achieve the proposed goals, an initial phase for assessing and updating the older design, building, and testing of SiGe modules (including both the electronics and casings) has been carried out. The results included demonstrate performances at logging GPS-L1 data with similar C/N0 and AGC values as the previous versions of the modules and offering navigation solutions with accuracies of a few meters. Secondly, a first iteration and design proposal for the new generation receiver has been proposed for GPS and GLONASS L1 and L2, which has been manufactured and tested. Partial tests have been performed due to the flaws of the current revision of the MicroZed Board in regards to its communication peripherals, and the results have validated the receiver’s design provided certain modifications are considered for future iterations. Furthermore, voltage and frequency tests have provided results with an error of less than 7%, and signal tests have provided C/N0 values similar to those of the SiGe modules of around 47[dB-Hz] which will be a useful baseline for future iterations. Finally, a design proposal for an Interface Board used between the older NT1065_PMOD Board and other FPGA boards carrying the standardized FMC connectors has been added to the report and negotiations with manufacturers have been engaged. gnss gps galileo glonass beidou constellation receiver new generation 4-channel design pcb shield front end nt1065 biastee bias t bias tee sma saw filter fpga microzed microheader digital analog lvds single end agc selector Telecommunications Telekommunikation Signal Processing Signalbehandling Communication Systems Kommunikationssystem

1

Page generated in 0.0386 seconds