Functional electrical stimulation (FES) devices have direct applications in the realm of rehabilitation engineering, physiotherapy, occupational therapy and medicine for research, diagnostic and therapeutic purposes. This thesis presents a novel electrical stimulator for use in a FES system. The stimulator produces regulated current pulses using two switched mode power supplies (SMPS) in series. The first power stage - a flyback converter - steps up the supply voltage using primary side digital control. The second power stage is a buck converter with output current hysteretic control. An output switched capacitor circuit shapes the current pulses. All pulse variables are programmable and various pulses can be formed for virtually any FES application. Compared to previous FES devices, the pulses generated here are sharper, have faster rise time and the amplitude and temporal characteristics are more tightly regulated. A single channel prototype system is implemented and experimental results are shown.

Functional electrical stimulation (FES) devices have direct applications in the realm of rehabilitation engineering, physiotherapy, occupational therapy and medicine for research, diagnostic and therapeutic purposes. This thesis presents a novel electrical stimulator for use in a FES system. The stimulator produces regulated current pulses using two switched mode power supplies (SMPS) in series. The first power stage - a flyback converter - steps up the supply voltage using primary side digital control. The second power stage is a buck converter with output current hysteretic control. An output switched capacitor circuit shapes the current pulses. All pulse variables are programmable and various pulses can be formed for virtually any FES application. Compared to previous FES devices, the pulses generated here are sharper, have faster rise time and the amplitude and temporal characteristics are more tightly regulated. A single channel prototype system is implemented and experimental results are shown.

Digitally-controlled, high power universal telecommunication power supply modules have been developed. In this work, the converter control strategy, and its design and implementation first, by means of parallel-operated, dual, 8-bit microcontrollers, and then by using a high processing power digital signal processor (DSP) have been emphasized. The proposed dual-processor based digital controller provides an extended operating output voltage range of the power supplies, user programmable current limit setting, serial communication based active load current sharing with automatic master-slave selection among parallel-operated modules, user selectable number of back-up battery cells, programmable temperature compensation curves, and automatic derating without extra hardware requirement. Overload and output short-circuit protection features are also controlled by software. One of the processors in the digital controller is employed for user interface purposes such as long term records, display, and alarm facilities, and remote control, which are inherently slow processes. The fast processing speed required by output voltage setting, current limit, and load current sharing however is to be fulfilled by a second processor dedicated to the adjustment of output voltages of modules. Tight dynamic load regulation requirement of a telecommunication power supply has been fulfilled by a 150 MIPS DSP, in place of a low cost, 8-bit microcontroller. The implemented digitally-controlled, 1.8 kW, 0-70V telecommunication power supplies have been tested successfully in several locations in the field.

This thesis presents System Identification based On-Line Health Monitoring to analyse the dynamic behaviour of the Switch-Mode Power Converter (SMPC), detect, and diagnose anomalies in passive electronic components. The anomaly detection in this research is determined by examining the change in passive component values due to degradation. Degradation, which is a long-term process, however, is characterised by inserting different component values in the power converter. The novel health-monitoring capability enables accurate detection of passive electronic components despite component variations and uncertainties and is valid for different topologies of the switch-mode power converter. The need for a novel on-line health-monitoring capability is driven by the need to improve unscheduled in-service, logistics, and engineering costs, including the requirement of Integrated Vehicle Health Management (IVHM) for electronic systems and components. The detection and diagnosis of degradations and failures within power converters is of great importance for aircraft electronic manufacturers, such as Thales, where component failures result in equipment downtime and large maintenance costs. The fact that existing techniques, including built-in-self test, use of dedicated sensors, physics-of-failure, and data-driven based health-monitoring, have yet to deliver extensive application in IVHM, provides the motivation for this research ... [cont.].

This master’s thesis work deal with diagnosis parameters immunity curves uniphase appliance on short - term voltage dips a interuption. Immunity curve is dependence smallest possible sizes RMS voltage for performance given to criteria function on time continuation voltage event. Curves of resistance is different for each electric appliance, and depending on the size and over-voltage network, the burden on resources and voltage during the event.. The goal of this work is to devise a methodology for measuring the implementation of parametric measurement limit curves of resistance for selected types of appliances.

<p>The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation.</p><p>The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done.</p><p>The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W.</p><p>A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.</p>

In this thesis a multifunctional DC/DC converter board will be developed for utilization as an educational experiment set in the switched-mode power conversion laboratory of power electronic courses. The board has a generic power-pole structure allowing for easy configuration of various power converter topologies and includes buck, boost, buck-boost, flyback, and forward converter topologies. All the converters can be operated in the open-loop control mode with a switching frequency range of 30-100 kHz and a maximum output power of 20 W. Also the buck converter can be operated in voltage mode control and the buck-boost converter can be operated in peak-current-mode control for the purpose of demonstrating the closed loop control performance of DC/DC converters. The designed board allows for experimentation on the DC/DC converters to observe the macroscopic (steadystate/ dynamic, PWM cycle and low frequency) and microscopic (switching dynamic) behavior of the converters. In the experiments both such characteristics can be clearly observed such that students at basic learning level (involving only the macroscopic behavior), and students at advanced learning level (additionally involving the parasitic effects) can benefit from the experiments. The thesis reviews the switch mode conversion principles, gives the board design and proceeds with the experiments illustrating the capabilities of the experimental system.

The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation. The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done. The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W. A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.