A coarse-grain parallel multi-block algorithm was designed for CHEQNS - a multi-block solver for solving chemically reacting flows in local chemical equilibrium and has been implemented using the Message Passing Interface (MPI). The parallel implementation confirms to the Single Program Multiple Data (SPMD) model. The parallel implementation uses synchronous update of fluxes across the block-block boundaries. The solution algorithm consists of block-decoupled Gauss-Seidel iterations. The coupling between the sub-domains on different processors occurs at the Newton iteration level. The parallel implementation is general and can accept an arbitrary arrangement of blocks in multi-block configuration with multiple blocks per processor. The parallel implementation has been verified against the results from the sequential multi-block solver for different types of flows. The parallel performance has been studied in terms of speed-up and efficiency. The influence of parallelization on the convergence was also studied.

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Design and analysis of a system consisting of a variable-speed synchronous generator that supplies an active dc load (inverter) through a three-phase diode rectifier requires adequate modeling in both time and frequency domain. In particular, the system's control-loops, responsible for stability and proper impedance matching between generator and load, are difficult to design without an accurate small-signal model. A particularity of the described system is strong non-ideal operation of the diode rectifier, a consequence of the large value of generator's synchronous impedance. This non-ideal behavior influences both steady state and transient performance. This thesis presents a new, average model of the system. The average model accounts, in a detailed manner, for dynamics of generator and load, and for effects of the non-ideal operation of diode rectifier. The model is non-linear, but time continuous, and can be used for large- and small-signal analysis. The developed model was verified on a 150 kW generator set with inverter output, whose dc-link voltage control-loop design was successfully carried out based on the average model. / Master of Science

In review, the author is struck with a feeling of the relative insignificance of his findings. Other sources of information seem to have a wealth of ideas, a scope far beyond the present investigation, and a variety of means to approach the subject. Upon further consideration, however, and a realization of the comparative expenditures of time, energy, and thought given to the subject, much familiarity has been gained with the general problem, with the factors involved, and their relative importance. Some interesting experiments have been watched, and the groundwork has been laid for more. In this light, the original purpose has been accomplished. / Master of Science

As embedded software and platforms become more complicated, many safety properties are left to simulation and testing. MRICDF is a formal polychronous language used to guarantee certain safety properties and alleviate the burden of software development and testing. We propose real-time extensions to MRICDF so that temporal properties of embedded systems can also be proven. We adapt the extended precedence encoding technique of Prelude and expand upon current schedulability analysis techniques for multi-periodic real-time systems. / Master of Science

The power consumption of smart camera in car black box varies significantly between light load and heavy load. The high efficiency voltage regulator is necessary in prolong the life of smart camera battery. Since the smart camera only recording the video when car is driving, the most time of the smart camera works in the sleep mode. Hence the light load efficiency is important in this application, however, conventional buck converter usually have high efficiency at heavy load but poor efficiency at light load. To increase the light load efficiency of buck converter, this research continues Yeago's two phase buck converter with optimum phase selection control and Zhao's two mode buck converter to further improve the light load efficiency for the target application. With 5V input voltage and 1.2V output voltage, the proposed two-mode synchronous buck converter can supply the load power from 12mW to 1.44W. To improve the light load efficiency of conventional buck converter, the proposed design applied Wei's baby buck concept to provide another light load power stage to reduce the switching loss and driving loss at light load. Then, the variable frequency ripple-based constant on-time control with discontinuous conduction mode (DCM) in light load is applied to the baby-buck mode to reduce the switching frequency to further reduce the switching loss. Also, the baby-buck mode uses the synchronous buck topology to remove the diode in asynchronous converter to increase the efficiency at light load. Finally, a sensorless mode selector remove the sensing resistor in power stage to increase the efficiency for entire load range, especially for the heavy load. The mode selector can select the optimum mode for different load condition, and the opposite mode would completely shut down to save the loss. The proposed design is implement in CMOS 0.25um technology. The proposed monolithic buck converter which include the power stage of heavy buck mode, baby-buck mode and the controller is fabricated. The measurement result shows the close loop efficiency varies from 70%-83% toward the entire load range. / Master of Science

This research explores two issues when implementing drain-source voltage sensed synchronous rectification (SR) on LLC DC-Transformers (DCXs). Firstly, a current resonance issue caused by the SR controller, and secondly a early turn-off issue from parasitics present in the drain-source sensing path. Two novel methods are proposed to solve the early turn-off issue, and an FPGA based solution is built to validate and fix the resonance issue. Simulations are run to quantify the amount of rectifier power savings possible with the proposed solutions. / Master of Science / This research explores issues and improvements in synchronous rectifiers used in resonant based power conversion circuits. The two issues explored hurt rectifier efficiency, and thus total power conversion circuit efficiency. Implementation issues are identified, simulated, and new solutions are proposed. Simulations are run to quantify the amount of power savings is possible.

La plupart des systèmes critiques sont dits «temps-réel durs» puisqu'ils requièrent des garanties temporelle fortes. Ces systèmes sont de plus en plus complexes et les processeurs mono-coeurs traditionnels ne sont plus assez puissants. Les multi-coeurs et les pluri-coeurs sont des alternatives plus puissantes, cependant ils contiennent des ressources partagées. Les accès concurrents à ces ressources provoquent des interférences qui doivent être prises en compte puisqu'elles rendent les délais d'accès non prédictibles. Pour les pluri-coeur, le réseau sur puce (NoC) doit être configuré pour éviter les interblocages et garantir des pires temps de traversée précis. Le MPPA2 de Kalray est un pluri-coeur avec de bonnes propriétés temporelles.Les langages Synchrones flot de données tels que Lustre ou Scade sont largement utilisés dans l'industrie aéronautique. Les programmes sont des réseaux de noeuds de calcul communicants. Nous présentons une méthode pour extraire le parallélisme des programmes Synchrones. Nous générons du code pour déployer les tâches parallèles sur la puce et pour implémenter les communications en mémoire partagée ou à travers le NoC. Notre solution permet la traçabilité du code. Elle est basée sur un modèle d'exécution dirigé par le temps où chaque tâche a une date de début. L'ordonnancement est statique et minimise les interférences grâce à l'utilisation de bancs mémoire. Une borne de pire temps d'exécution (WCET) est calculée. Elle inclut les interférences mémoire et les pires temps de traversée NoC. Nous générons la configuration du processeur qui permet une allocation équitable des bandes passantes sur le NoC, la garantie de temps de traversées bornés et la synchronisation des horloges. Enfin, nous appliquons notre outils sur des exemples de programmes aéronautiques et un exemple synthétique utilisant 64 coeurs. / Most critical systems are subject to hard real-time requirements. These systems are more and more complex and the computational power of the predictable single-core processors is no longer sufficient. Multi- or many-core architectures are good alternatives but interferences on shared resources must be taken into account to avoid unpredictable timing effects. For many-core, the Network-on-Chip (NoC) must be configured such that deadlocks are avoided and a tight Worst Case Traversal Time (WCTT) of the communications can be computed. The Kalray MPPA2 is a many-core architecture with good timing properties.Dataflow Synchronous languages such as Lustre or Scade are widely used for avionics critical software. In these languages, programs are described by networks of computational nodes. We introduce a method to extract parallel tasks from synchronous programs. Then, we generate parallel code to deploy tasks on the chip and implement NoC and shared-memory communications. The generated code enables traceability. It is based on a time-triggered execution model which relies on a static schedule and minimizes the memory interferences thanks to usage of memory banks. The code enables the computation of a worst case execution time bound accounting for the memory interferences and the WCTT of NoC transmissions. We generate a configuration of the platform to enable a fair bandwidth attribution on the NoC, bounded transmissions through the NoC and clock synchronization. Finally, we apply this toolchain on avionic case studies and synthetic benchmarks running on 64 cores.

Though, most of online courses conducted in the pass were asynchronous oriented, due to the recent advance of information technology on the Internet bandwidth and the IP-based conferencing system, conducting synchronous online courses are now feasible. There are no longer obstacles for promoting e-learning in terms of limited computing power, short memory capacity and not enough network bandwidth. The new challenges have shifted to how to conduct a high qualify online course by combing synchronous and asynchronous learning into a blended mode. The feature of asynchronous-oriented instruction and the text only interaction mode in the passed e-learning are very inconvenient and inefficient. Because Chinese input for many senior teachers are difficult and using text express the meaning of content and answer questions would result bad performance of demonstrating instructors¡¦ professional. The advanced Learning Management System nowadays can support IP-based video-conferencing and document sharing for teachers and students to do online synchronous face to face instruction and interactions; the question is most teachers are not aware of this kind of potential and what kind of teaching models can be adopted in the online synchronous classroom. The purpose of this thesis is to explore different teaching models and their best practices by action research, such that the results can serve as good references for teachers. This research environment is the course named e-Learning Theory & Practice conduced for many semesters on NSYSU Cyber University.