abstract: Using historical data from the third-party payment acquiring industry, I develop a statistical model to predict the probability of fraudulent transactions by the merchants. The model consists of two levels of analysis – the first focuses on fraud detection at the store level, and the second focuses on fraud detection at the merchant level by aggregating store level data to the merchant level for merchants with multiple stores. My purpose is to put the model into business operations, helping to identify fraudulent merchants at the time of transactions and thus mitigate the risk exposure of the payment acquiring businesses. The model developed in this study is distinct from existing fraud detection models in three important aspects. First, it predicts the probability of fraud at the merchant level, as opposed to at the transaction level or by the cardholders. Second, it is developed by applying machine learning algorithms and logistical regressions to all the transaction level and merchant level variables collected from real business operations, rather than relying on the experiences and analytical abilities of business experts as in the development of traditional expert systems. Third, instead of using a small sample, I develop and test the model using a huge sample that consists of over 600,000 merchants and 10 million transactions per month. I conclude this study with a discussion of the model’s possible applications in practice as well as its implications for future research. / Dissertation/Thesis / Doctoral Dissertation Business Administration 2015

Energy consumption is one of the most constrained requirements for the development and implementation of wireless sensor networks. Many design aspects affect energy consumption, ranging from the hardware components, operations of the sensors, the communication protocols, the application algorithms, duty cycles and others. Efficient simulation tool can be used to estimate the contribution to energy consumption of all of these factors, and significantly decrease the efforts and time spent to choose the right solution that fits best to a particular application. In this work we present design space exploration methodology for ultra low power embedded systems and wireless sensor networks. The methodology takes inspiration from Platform Based Design (PBD) paradigm and defines separate abstraction layers for all system aspects that directly contribute power consumption of target applications. To support presented methodology we built a SystemC-based discrete event simulation framework, called “PASES”, that provides power-aware simulation and analysis of wireless sensor networks and sensor nodes. Its modular architecture allows flexible, extensible and rapid modeling of custom HW platforms, SW application models, communication protocols, energy sources, environment dynamics and nodes mobility. Based on the feedback gained from PASES, the optimal and energy-efficient solution for the specific project of interest can be selected. The proposed approach improves state-of-the-art by providing fast and reliable power-aware system-level exploration for a wide range of custom applications

No description available.

The difficulties of system design are persistentlyincreasing due to the integration of more functionality on asystem, time-to-market pressure, productivity gap, andperformance requirements. To address the system designproblems, design methodologies build system models at higherabstraction level. However, the design task to map an abstractfunctional model on a system architecture is nontrivial becausethe architecture contains a wide variety of system componentsand interconnection topology, and a given functionality can berealized in various ways depending on cost-performancetradeoffs. Therefore, a system design methodology must provideadequate design steps to map the abstract functionality on adetailed architecture. MASIC—Maths to ASIC—is a system design methodologytargeting DSP applications. In MASIC, we begin with afunctional model of the system. Next, the architecturaldecisions are captured to map the functionality on the systemarchitecture. We present a systematic approach to classify thearchitectural decisions in two categories: system leveldecisions (SLDs) and implementation level decisions (ILDs). Asa result of this categorization, we only need to consider asubset of the decisions at once. To capture these decisions inan abstract way, we present three transaction level models(TLMs) in the context of DSP systems. These TLMs capture thedesign decisions using abstract transactions where timing ismodeled only to describe the major synchronization events. As aresult the functionality can be mapped to the systemarchitecture without meticulous details. Also, the artifacts ofthe design decisions in terms of delay can be simulatedquickly. Thus the MASIC approach saves both modeling andsimulation time. It also facilitates the reuse of predesignedhardware and software components. To capture and inject the architectural decisionsefficiently, we present the grammar based language of MASIC.This language effectively helps us to implement the stepspertaining to the methodology. A Petri net based simulationtechnique is developed, which avoids the need to compile theMASIC description to VHDL for the sake of simulation. We alsopresent a divide and conquer based approach to verify the MASICmodel of a system. Keywords:System design methodology, Signal processingsystems, Design decision, Communication, Computation, Modeldevelopment, Transaction level model, System design language,Grammar, MASIC.

<p>The difficulties of system design are persistentlyincreasing due to the integration of more functionality on asystem, time-to-market pressure, productivity gap, andperformance requirements. To address the system designproblems, design methodologies build system models at higherabstraction level. However, the design task to map an abstractfunctional model on a system architecture is nontrivial becausethe architecture contains a wide variety of system componentsand interconnection topology, and a given functionality can berealized in various ways depending on cost-performancetradeoffs. Therefore, a system design methodology must provideadequate design steps to map the abstract functionality on adetailed architecture.</p><p>MASIC—Maths to ASIC—is a system design methodologytargeting DSP applications. In MASIC, we begin with afunctional model of the system. Next, the architecturaldecisions are captured to map the functionality on the systemarchitecture. We present a systematic approach to classify thearchitectural decisions in two categories: system leveldecisions (SLDs) and implementation level decisions (ILDs). Asa result of this categorization, we only need to consider asubset of the decisions at once. To capture these decisions inan abstract way, we present three transaction level models(TLMs) in the context of DSP systems. These TLMs capture thedesign decisions using abstract transactions where timing ismodeled only to describe the major synchronization events. As aresult the functionality can be mapped to the systemarchitecture without meticulous details. Also, the artifacts ofthe design decisions in terms of delay can be simulatedquickly. Thus the MASIC approach saves both modeling andsimulation time. It also facilitates the reuse of predesignedhardware and software components.</p><p>To capture and inject the architectural decisionsefficiently, we present the grammar based language of MASIC.This language effectively helps us to implement the stepspertaining to the methodology. A Petri net based simulationtechnique is developed, which avoids the need to compile theMASIC description to VHDL for the sake of simulation. We alsopresent a divide and conquer based approach to verify the MASICmodel of a system.</p><p><b>Keywords:</b>System design methodology, Signal processingsystems, Design decision, Communication, Computation, Modeldevelopment, Transaction level model, System design language,Grammar, MASIC.</p>

Parallelizing the development cycles of hardware and software is becoming the industry’s norm for reducing time to market for electronic devices. In the absence of hardware, software development is based on a virtual platform; a fully functional software model of a system under development, able to execute unmodified code. A Transaction Level Model, expressed with the SystemC TLM 2.0 language, is one of the many possible ways for constructing a virtual platform. Under SystemC’s simulation engine, hardware and software is being co-simulated. However, the sequential nature of the reference implementation of the SystemC’s simulation kernel, is a limiting factor. Poor simulation performance often constrains the scope and depth of the design decisions that can be evaluated. It is the main objective of this thesis’ project to demonstrate the feasibility of parallelizing the co-simulation of hardware and software using Transaction Level Models, outside SystemC’s reference simulation environment. The major obstacle identified is the preservation of causal relations between simulation events. The solution is obtained by using the process synchronization mechanism known as the Chandy/Misra/Bryantt algorithm. To demonstrate our approach and evaluate under which conditions a speedup can be achieved, we use the model of a cache-coherent, symmetric multiprocessor executing a synthetic application. Two versions of the model are used for the comparison; the parallel version, based on the Message Passing Interface 3.0, which incorporates the synchronization algorithm and an equivalent sequential model based on SystemC TLM 2.0. Our results indicate that by adjusting the parameters of the synthetic application, a certain threshold is reached, above which a significant speedup against the sequential SystemC simulation is observed. Although performed manually, the transformation of a SystemC TLM 2.0 model into a parallel MPI application is deemed feasible.

The present work aims to provide a contribution to improve the efficiency the design flow of integrated systems, focusing, specifically, on the performance evaluation of its communication structures. The use of Transaction Level Modeling (TLM) is proposed, in order to take advantage of the reduction of design effort and time. Within the performance evaluation approaches, the utilization of traffic generators instead of full system simulations started to be adopted due to its higher time efficiency. Initial works on on-chip traffic generation focused on Poisson processes and classic Markovian models, which are unable to capture Long Range Dependence (LRD). This fact led to the adoption of fractal/self-similar models. Later advancements have shown that the traffic produced in multiprocessed systems can show higher degrees of complexity, what can be attributed to the presence multifractal characteristics. In this work, a methodology to evaluate the on-chip traffic and to the development of a transaction level traffic generator is proposed. The main contributions of this work are a detailed analysis of traffic time series obtained by TLM simulations and the study of the effects of the traffic generator on these simulations, concerning, mainly, the speedup-accuracy trade-off. The proposed analysis follow the multifractal paradigm, allowing system developers to (1) understand the statistical nature of on-chip traffic, (2) to obtain accurate representations of this traffic and (3) to build traffic generators that mimic processing elements realistically. Another contribution of this work is a comparison of the performance, considering the accuracy of the obtained synthetic traffic time series, between monofractal and multifractal models. All of the mentioned contributions were grouped throughout the detailed methodology presented on the present document, for which experiments were carried out. / O presente trabalho visa oferecer uma contribuição para o aumentar a eficiência do fluxo de projeto de sistemas integrados, focando, especificamente, na avaliação do desempenho de suas estruturas de comunicação. É proposta a utilização de simulações com modelos no nível de transações (TLM), com o objetivo de se obter vantagens da redução de esforço e tempo de projeto oferecidos por esta abordagem. Dentro das propostas de análise de desempenho, a utilização de geradores de tráfego ao invés simulações de sistema completo tem sido adotada devido a sua maior eficiência no tempo. Trabalhos iniciais na geração de tráfego intrachip focaram-se em processos de Poisson e em modelos de Markov clássicos, os quais não capturam Dependência de Longa Duração (LRD). Este fato levou a adoção de modelos fractais/auto-similares. Avanços posteriores mostraram que o tráfego produzido pelos elementos de sistemas multiprocessados podem apresentar maior grau de complexidade, que pode ser atribuída à presença de características multifractais. Neste trabalho, é proposta uma metodologia para a avaliação de tráfego intrachip para o desenvolvimento de um gerador de tráfego TLM. As principais contribuições deste trabalho são uma análise detalhada das séries temporais de tráfego obtidas nas simulações TLM e o estudo dos efeitos que o gerador de tráfego exerce sobre estas simulações, se concentrando, principalmente, na relação entre precisão e aceleração da simulação. As análises propostas se baseiam no paradigma multifractal, o qual permite (1) um maior entendimento da natureza estatística do tráfego pelos desenvolvedores de sistemas, (2) a obtenção de uma representação precisa deste tráfego e (3) a construção de geradores de tráfego que substituam elementos processantes de maneira realista. Outra contribuição deste trabalho é a comparação do desempenho, no que concerne a precisão das séries de tráfego sintéticas obtidas, de modelos monofractais e multifractais. Todas as contribuições mencionadas foram agrupadas na metodologia detalhada, apresentada no presente documento, sobre a qual experimentos foram realizados.

Este trabalho visa dar uma contribuição para o aumento de eficiência no fluxo de projeto de sistemas integrados, especificamente na avaliação de desempenho da comunicação entre os seus blocos componentes. É proposto o uso de modelagem e simulação de hardware em alto nível, no nível de transações, denominado TLM, para aproveitar a redução de esforço e tempo que se pode oferecer ao projeto de sistemas integrados, diferentemente de enfoques convencionais em níveis mais baixos de descrição, como o nível de registradores (RTL). É proposta uma forma de análise do tráfego intrachip produzido na comunicação de elementos do sistema, visando-se o uso dos resultados obtidos para descrição de geradores de tráfego. A principal contribuição deste trabalho é a proposta da análise de séries de tráfego obtido durante simulação de plataformas de hardware descritas no nível TLM usando-se métodos estatísticos conhecidos da área de estudo de séries temporais. A análise permite ao projetista ter maior compreensão da natureza estatística do tráfego intrachip, denominada dependência de curta ou longa duração (SRD e LRD), para o posterior ajuste de modelos usados na geração de séries sintéticas que representem tal natureza. Os resultados da análise mostraram que o tráfego obtido por simulação TLM tem natureza similar em relação ao da do tráfego obtido por simulação num nível mais baixo de abstração, do tipo de precisão por ciclos, indicando que o tráfego TLM pode ser usado para a representação do tráfego intrachip. Outra contribuição deste trabalho é a proposta de ajuste de modelos paramétricos autossimilares usando-se a decomposição da série de tráfego original, tendo sido feita uma comparação dos resultados desta com o ajuste convencional feito a modelos sem decomposição. Estas contribuições foram agrupadas dentro de uma metodologia detalhada, apresentada neste documento, para a qual experimentos foram realizados. Os resultados a partir das séries sintéticas autossimilares geradas pelos modelos estimados, apresentaram semelhança nos indicadores de SRD e LRD em relação às séries originais TLM, mostrando ser favorável o uso futuro destas séries sintéticas na implementação de geradores de tráfego. / It is objective of this work to make a contribution to improve the efficiency of the integrated systems design flow, specifically on the evaluation of communication performance between component blocks. The use of high level hardware modeling and simulation, at the transaction level, known as TLM, is proposed, in order to take advantage of the reduction of effort and time for the integrated system design; that in contrast to the traditional approaches, which use lower hardware description level, such as register transfer level (RTL). A methodology to evaluate the intra-chip traffic produced by the communication between system elements is proposed. The main contribution of this work is the analysis of traffic time series obtained by simulation of hardware platforms modeled in TLM, using well-known statistical methods for time series analysis. The analysis allows the system developer to understand the statistical nature of the intra-chip traffic, also known as short and long range dependence (SRD and LRD), for later adjustment and accurate representation of the traffic nature in synthetic series. The analysis results have shown that traffic traces obtained by TLM simulation has similar statistical nature as the traffic traces obtained at lower abstraction level, as cycle accurate type, which indicates that TLM traffic could be used to represent intrachip traffic. Another contribution of this work is a fitting procedure to auto similar parametric models thought the decomposition of the original traffic, and its comparison to the results of the conventional fitting, when applied to models that are not decomposed. These contributions were grouped and included in the detailed methodology presented in this document, being a series of experiments carried out. The results related to self-similar synthetic series, obtained from the fitted models, have shown similarity to the SRD and LRD indicators of the original TLM series, what favors the use of synthetic series future for the implementation of traffic generators.

Cette thèse porte sur la modélisation des systèmes-sur-puce au niveau transactionnel, une approche connue sous le nom de prototypage virtuel. Les prototypes virtuels sont d'un grand intérêt industriel parce qu'ils permettent de démarrer certaines activités (telles que le développement du logiciel embarqué) plus tôt dans le flot de conception. Du fait que cette approche est relativement nouvelle, un grand nombre de problèmes de modélisation sont encore ouverts. En particulier, il est essentiel de comprendre à quel point un modèle donné est proche du système hypothétique qu'il est sensé représenter. C'est un problème difficile car nous n'avons pas les moyens de réaliser une comparaison objective, vu que le système modélisé n'est pas disponible physiquement au moment de la modélisation. Nous avons besoin d'une méthodologie pour traiter ces difficultés, qui s'étendent au-delà de simples exigences objectives et de l'analyse de besoin fonctionnel. Dans ce contexte, l'industrie cherche des directives de modélisation claires, fondées sur l'expérience et l'identification des pratiques actuelles et des problèmes récurrents. Dans cette thèse, nous présentons une étude compréhensive d'un large éventail de considérations techniques impliquées dans le flot de conception du logiciel et du matériel qui constituent un système-sur-puce typique. Nous utilisons ces connaissances pour identifier une source particulière de divergence entre le modèle et le système modélisé. Nous montrons que cette divergence masque certains bogues du logiciel sur le prototype virtuel. Nous mettons en évidence la pratique de modélisation à l'origine de cette situation. Deuxièmement, nous essayons d'identifier des problèmes liés à l'utilisation du langage de modélisation dans les pratiques actuelles. Nous prétendons que, d'une part, ces problèmes sont dûs à la confusion entre les concepts de la modélisation transactionnelle et leur implémentation dans le langage standard de l'industrie ; et d'autre part que ce n'est qu'en menant des comparaisons avec un autre langage que l'on pourrait quantifier leur étendue. Pour ce faire, nous proposons un cadre d'application spécialement conçu pour guider l'étude des concepts fondamentaux de la modélisation transactionnelle. Entre autres, nous introduisons une nouvelle méthode pour la modélisation du temps dans les simulateurs à événements discrets. Cette méthode dévoile la différence entre une action instantanée et une tâche avec durée. Ensuite, elle l'exploite de plusieurs manières : pour enrichir les outils de visualisation de traces ; pour dériver une définition claire de chevauchement de tâches ; pour accélérer la simulation à moindre effort, en parallélisant l'exécution d'actions se déroulant à des temps simulés différents ; et pour révéler des bogues subtiles en tenant compte du fait que les actions à des temps simulés différents ne sont pas forcément synchronisées. / This thesis deals with modeling of Systems-on-a-Chip (SoC) at the Transactional Level (TLM), an approach also known as virtual prototyping. Virtual prototypes are of special industrial interest because they allow some activities (such as embedded software development) to start earlier in the design flow. Because this approach is relatively new, several modeling issues are still open. In particular, there is an increasing need for understanding how close a given model is to the hypothetical system it is intended to represent. This is a difficult problem specially because we lack a way to perform an objective comparison, since the modeling activity is prior to the physical existence of the modeled system. A methodology is required to address these concerns, going beyond classical objective and functional quality requirements. In this context, the industry searches for clear modeling guidelines based on experience and the identification of the current modeling practices and known recurring problems. In this thesis, we present a comprehensive study of a range of technical considerations involved in the design flow of the hardware and software that constitutes a typical SoC. We use this knowledge to identify one particular source of divergence between the model and the modeled system. We show that this divergence causes some software bugs to become hidden in the virtual prototype and we correlate this situation to the corresponding modeling practice. Secondly, we attempt to identify language-dependency issues in the modeling practices. We claim that it is only by confronting with an alternative language that we could measure the extent to which common modeling issues were caused by mixing up conceptual transaction-level modeling with its implementation in the current industry standard language. Therefore, we propose a complete experimentation framework specifically designed to help in the study of fundamental concepts beneath TLM. Amongst other features, this framework introduces a novel approach to modeling time in discrete-event simulators that distinguishes between instantaneous actions and tasks that take time. We show that this notion can be exploited to enrich trace visualization tools; to derive a clear definition of overlapping tasks; to effortlessly achieve an important simulation speedup by enabling parallel execution of actions occurring at different simulation times; and to expose subtle bugs by removing the constraint that actions at different simulation times are necessarily synchronized.

The present work aims to provide a contribution to improve the efficiency the design flow of integrated systems, focusing, specifically, on the performance evaluation of its communication structures. The use of Transaction Level Modeling (TLM) is proposed, in order to take advantage of the reduction of design effort and time. Within the performance evaluation approaches, the utilization of traffic generators instead of full system simulations started to be adopted due to its higher time efficiency. Initial works on on-chip traffic generation focused on Poisson processes and classic Markovian models, which are unable to capture Long Range Dependence (LRD). This fact led to the adoption of fractal/self-similar models. Later advancements have shown that the traffic produced in multiprocessed systems can show higher degrees of complexity, what can be attributed to the presence multifractal characteristics. In this work, a methodology to evaluate the on-chip traffic and to the development of a transaction level traffic generator is proposed. The main contributions of this work are a detailed analysis of traffic time series obtained by TLM simulations and the study of the effects of the traffic generator on these simulations, concerning, mainly, the speedup-accuracy trade-off. The proposed analysis follow the multifractal paradigm, allowing system developers to (1) understand the statistical nature of on-chip traffic, (2) to obtain accurate representations of this traffic and (3) to build traffic generators that mimic processing elements realistically. Another contribution of this work is a comparison of the performance, considering the accuracy of the obtained synthetic traffic time series, between monofractal and multifractal models. All of the mentioned contributions were grouped throughout the detailed methodology presented on the present document, for which experiments were carried out. / O presente trabalho visa oferecer uma contribuição para o aumentar a eficiência do fluxo de projeto de sistemas integrados, focando, especificamente, na avaliação do desempenho de suas estruturas de comunicação. É proposta a utilização de simulações com modelos no nível de transações (TLM), com o objetivo de se obter vantagens da redução de esforço e tempo de projeto oferecidos por esta abordagem. Dentro das propostas de análise de desempenho, a utilização de geradores de tráfego ao invés simulações de sistema completo tem sido adotada devido a sua maior eficiência no tempo. Trabalhos iniciais na geração de tráfego intrachip focaram-se em processos de Poisson e em modelos de Markov clássicos, os quais não capturam Dependência de Longa Duração (LRD). Este fato levou a adoção de modelos fractais/auto-similares. Avanços posteriores mostraram que o tráfego produzido pelos elementos de sistemas multiprocessados podem apresentar maior grau de complexidade, que pode ser atribuída à presença de características multifractais. Neste trabalho, é proposta uma metodologia para a avaliação de tráfego intrachip para o desenvolvimento de um gerador de tráfego TLM. As principais contribuições deste trabalho são uma análise detalhada das séries temporais de tráfego obtidas nas simulações TLM e o estudo dos efeitos que o gerador de tráfego exerce sobre estas simulações, se concentrando, principalmente, na relação entre precisão e aceleração da simulação. As análises propostas se baseiam no paradigma multifractal, o qual permite (1) um maior entendimento da natureza estatística do tráfego pelos desenvolvedores de sistemas, (2) a obtenção de uma representação precisa deste tráfego e (3) a construção de geradores de tráfego que substituam elementos processantes de maneira realista. Outra contribuição deste trabalho é a comparação do desempenho, no que concerne a precisão das séries de tráfego sintéticas obtidas, de modelos monofractais e multifractais. Todas as contribuições mencionadas foram agrupadas na metodologia detalhada, apresentada no presente documento, sobre a qual experimentos foram realizados.