<p dir="ltr">Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional complimentary metal-oxide-semiconductor (CMOS)-based logic in a variety of applications ranging from Bayesian inference to combinatorial optimization, and invertible Boolean logic. These applications, which have found use in the rapidly growing fields of machine learning and artificial intelligence, are traditionally computationally-intensive and so make the push for novel computing schemes that are intrinsically low-power and scalable all the more urgent.</p><p dir="ltr">The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires <i>tunable </i>stochasticity; low-barrier nanomagnets, in which the magnetic moment fluctuates randomly and continuously due to the presence of thermal energy, are a natural vehicle for providing the core functionality required. This dissertation describes the work done in mining the rich field of spintronics to produce devices that can act as natural hardware accelerators for probabilistic computing algorithms.</p><p dir="ltr">First, experiments exploring Fe₃O₄ nanoparticles as naturally stochastic systems are presented. Using NV center measurements on an array of such nanoparticles, it is shown that they fluctuate intrinsically at GHz frequencies at room temperature; these fluctuations could be harnessed to act as a stochastic noise source, and would, in principle, enable fast computation.</p><p dir="ltr">The focus then shifts to the development of a platform that allows for easier <i>electrical</i> readout: the low-barrier magnetic tunnel junction (MTJ). We show the work done in the development and characterization of these devices, how they respond to non-ideal environments, such as elevated temperatures and exposure to high-energy electromagnetic radiation, how their intrinsic stochasticity might be tuned with electrical currents and external magnetic fields, and then how these might be integrated with a simple transistor circuit to produce a compact low-energy implementation of a p-bit.</p><p dir="ltr">Next, by integrating our stochastic MTJs with 2D-MoS₂field-effect transistors (FETs), the first <i>on-chip </i>realization of a key p-bit building block, displaying voltage-controllable stochasticity, is demonstrated. This is followed by another key demonstration through the fabrication of stochastic MTJs directly on top of an integrated circuit platform, where the transistor circuitry is provided by 180nm-node CMOS technology.</p><p dir="ltr">In addition, supported by circuit simulations, this work provides a careful device-level analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component can influence the overall p-bit’s output. In particular, we show that – against common wisdom – a large tunnel magnetoresistance (TMR) is not the best choice for p-bits; bimodal telegraphic fluctuations are highly undesirable and are a sign of a slow device; and an ideal inverter with a large gain is unsuitable for p-bit applications due to the higher likelihood of unwanted plateaus in the resulting p-bit’s output.</p><p dir="ltr">This analysis is extended to consider the impact of such non-ideal p-bits when used to construct probabilistic circuits, with the focus on the emulation of the Boolean logic AND gate through a three p-bit correlated system. It is found that a probabilistic circuit made with ideal p-bits can accurately emulate the function of an AND gate, while the non-ideal p-circuits suffer from an increased error rate in emulating the AND gate’s truth table.</p><p dir="ltr">The understanding gained at the individual device level, in what makes a good or bad MTJ, to how the different components of the 3T-1MTJ p-bit can affect its output, and subsequently how non-ideal p-bits can impact circuit performance, can be important for the future realization of scaled on-chip p-bit networks.</p>

We present the development of a novel, UHV-compatible device fabrication strategy for the realisation of nano- and atomic-scale devices in silicon by harnessing the atomic-resolution capability of a scanning tunnelling microscope (STM). We develop etched registration markers in the silicon substrate in combination with a custom-designed STM/ molecular beam epitaxy system (MBE) to solve one of the key problems in STM device fabrication ??? connecting devices, fabricated in UHV, to the outside world. Using hydrogen-based STM lithography in combination with phosphine, as a dopant source, and silicon MBE, we then go on to fabricate several planar Si:P devices on one chip, including control devices that demonstrate the efficiency of each stage of the fabrication process. We demonstrate that we can perform four terminal magnetoconductance measurements at cryogenic temperatures after ex-situ alignment of metal contacts to the buried device. Using this process, we demonstrate the lateral confinement of P dopants in a delta-doped plane to a line of width 90nm; and observe the cross-over from 2D to 1D magnetotransport. These measurements enable us to extract the wire width which is in excellent agreement with STM images of the patterned wire. We then create STM-patterned Si:P wires with widths from 90nm to 8nm that show ohmic conduction and low resistivities of 1 to 20 micro Ohm-cm respectively ??? some of the highest conductivity wires reported in silicon. We study the dominant scattering mechanisms in the wires and find that temperature-dependent magnetoconductance can be described by a combination of both 1D weak localisation and 1D electron-electron interaction theories with a potential crossover to strong localisation at lower temperatures. We present results from STM-patterned tunnel junctions with gap sizes of 50nm and 17nm exhibiting clean, non-linear characteristics. We also present preliminary conductance results from a 70nm long and 90nm wide dot between source-drain leads which show evidence of Coulomb blockade behaviour. The thesis demonstrates the viability of using STM lithography to make devices in silicon down to atomic-scale dimensions. In particular, we show the enormous potential of this technology to directly correlate images of the doped regions with ex-situ electrical device characteristics.

We present the development of a novel, UHV-compatible device fabrication strategy for the realisation of nano- and atomic-scale devices in silicon by harnessing the atomic-resolution capability of a scanning tunnelling microscope (STM). We develop etched registration markers in the silicon substrate in combination with a custom-designed STM/ molecular beam epitaxy system (MBE) to solve one of the key problems in STM device fabrication ??? connecting devices, fabricated in UHV, to the outside world. Using hydrogen-based STM lithography in combination with phosphine, as a dopant source, and silicon MBE, we then go on to fabricate several planar Si:P devices on one chip, including control devices that demonstrate the efficiency of each stage of the fabrication process. We demonstrate that we can perform four terminal magnetoconductance measurements at cryogenic temperatures after ex-situ alignment of metal contacts to the buried device. Using this process, we demonstrate the lateral confinement of P dopants in a delta-doped plane to a line of width 90nm; and observe the cross-over from 2D to 1D magnetotransport. These measurements enable us to extract the wire width which is in excellent agreement with STM images of the patterned wire. We then create STM-patterned Si:P wires with widths from 90nm to 8nm that show ohmic conduction and low resistivities of 1 to 20 micro Ohm-cm respectively ??? some of the highest conductivity wires reported in silicon. We study the dominant scattering mechanisms in the wires and find that temperature-dependent magnetoconductance can be described by a combination of both 1D weak localisation and 1D electron-electron interaction theories with a potential crossover to strong localisation at lower temperatures. We present results from STM-patterned tunnel junctions with gap sizes of 50nm and 17nm exhibiting clean, non-linear characteristics. We also present preliminary conductance results from a 70nm long and 90nm wide dot between source-drain leads which show evidence of Coulomb blockade behaviour. The thesis demonstrates the viability of using STM lithography to make devices in silicon down to atomic-scale dimensions. In particular, we show the enormous potential of this technology to directly correlate images of the doped regions with ex-situ electrical device characteristics.

Cette thèse porte sur l’étude des courants de spin et de l’effet Hall de spin dans des nanostructureslatérales. Des vannes de spin latérales Py/Al, Py/Cu et Py/Au, ont été fabriquées parlithographie électronique, puis optimisées et caractérisées par des mesures de magnéto-transport.Des mesures non locales, de GMR, et d’effet Hanle ont ainsi été enregistrées à 300K et 77K. De l’optimisation des vannes de spin latérales a découlé l’observation de fortes amplitudes designal de spin. De plus, les effets du confinement latéral et vertical de l‘accumulation de spin,par utilisation d’un canal non-magnétique confiné ou de barrières tunnel AlOx, ont été mis enévidence expérimentalement et décrits théoriquement. Des simulations par éléments finis et desanalyses basées sur les modèles de diffusion 1D ont été développées, permettant l’extraction de lapolarisation effective Peff et de la longueur de diffusion de spin lNsf des données expérimentales.Enfin, l’effet Hall de spin dans des matériaux à fort angles de Hall (Pt, aliage d’Au) a étéétudié dans des hétérostructures latérales et par pompage de spin à la résonance ferromagnétique. / This PhD thesis focus on the study of spin currents and of the spin Hall effect in lateralnano-structures. Lateral spin-valves based on Py/Al, Py/Cu and Py/Au, fabricated by meansof electron-beam lithography, have been optimized and characterized using magneto-resistancemeasurements. Non-local, GMR and Hanle effect measurements have been recorded at 300K and77K. The optimization of these lateral spin-valves allowed the observation of high spin signalamplitudes. Lateral and vertical confinement effects on the spin accumulation, by using confinednon-magnetic channel and AlOx tunnel barriers, were evidenced experimentally and describedtheoretically. Finite Elements Method simulations and analyses based on a 1D diffusion modelhave been developed, allowing the extraction from our experimental data of the effective spinpolarization Peff and of the spin diffusion length lNsf .Finally, the spin Hall effect of materials with high spin Hall angles (Pt, Au alloys) has beenstudied using both hybrid lateral nano-structures and spin pumping ferro-magnetic resonance.