A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to replace the conventional PMOSFET for solving the problem of width compensation. Also, we carefully investigate and analyze the non-conventional CMOS characteristics with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load. According to the results, our proposed novel CMOS inverter has correct logic behavior and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL CMOS. In addition, because of the N-type output drain node and the SOI structure, our proposed CMOS does not need any physical isolation technique, thereby improving the packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1 % reduction in the total area when compared with the SOI-based CMOS. More importantly, due to the reduced process steps, the cost reduction can be achieved. We therefore believe that a high packing density novel CMOS inverter with reduced process steps can become one of the contenders for future CMOS scaling.

abstract: This study examines determinants of the length of conflict between firms and the Internal Revenue Service (IRS). I hand collect firm disclosures of the number of years open for federal tax purposes to create a proxy for IRS conflict length. Using this proxy, I find evidence that larger firms, firms with more book-tax differences, and firms facing higher IRS attention and audit probabilities are associated with lengthier IRS conflicts. In contrast, firms with higher deferred tax assets, intangibles, return on assets, and firms disclosing participation in the Compliance Assurance Process program are associated with shorter IRS conflicts. Additional analyses show IRS conflict length is positively associated with manager risk preferences and poor tax accounting quality. I also find lengthier IRS conflicts are associated with higher future tax risk and higher audit fees. Tax controversy is becoming increasingly important for firms but remains relatively understudied. I provide empirical evidence on cross-sectional variation in IRS conflict length. / Dissertation/Thesis / Doctoral Dissertation Accountancy 2020

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS). / QC 20111206

Les MOSFETs ultra-thin body UTB ont été fabriqués avec une technologie auto-alignée. Le canal conducteur est constitué d’InGaAs à 75% de taux d’indium ou d’un composite InAs/In0,53Ga0,47As. Une fine couche d'InP (3 nm) a été insérée entre le canal et l'oxyde, afin d’éloigner les défauts de l’interface oxyde-semiconducteur du canal. Enfin, une épaisseur de 4 nm d'oxyde de grille (Al2O3) a été déposée par la technique de dépôt des couches atomiques. Les contacts ohmiques impactent les performances des MOSFETs. La technologie UTB permet difficilement d’obtenir des contacts S/D de faibles résistances. De plus, l’utilisation de la technique d’implantation ionique pour les architectures UTB est incompatible avec le faible budget thermique des matériaux III-V et ne permet pas d’obtenir des contacts ohmiques de bonne qualité. Par conséquent, nous avons développé une technologie auto-alignée, basée sur la diffusion du Nickel « silicide-like » par capillarité à basse température de recuit (250°C) pour la définition des contacts de S/D. Finalement, nous avons étudié et analysé la résistance de l'alliage entre le Nickel et les III-V. A partir de cette technologie, des MOSFET In0,75Ga0,25As et InAs/In0,53Ga0,47As ont été fabriqués. On constate peu de différences sur les performances électriques de ces deux composants. Pour le MOSFET InAs/InGaAs ayant une longueur de grille LG =150 nm, un courant maximal de drain ID=730 mA/mm, et une transconductance extrinsèque maximale GM, MAX = 500 mS/mm ont été obtenu. Le dispositif fabriqué présente une fréquence de coupure fT égale à 100 GHz, et une fréquence d'oscillation maximale fmax de 60 GHz, pour la tension drain-source de 0,7 V. / Abstract : Silicon-based devices dominate the semiconductor industry because of the low cost of this material, its technology availability and maturity. However, silicon has physical limitations, in terms of mobility and saturation velocity of the carriers, which limit its use in the high frequency applications and low supply voltage i.e. power consumption, in CMOS technology. Therefore, III-V materials like InGaAs and InAs are good candidates because of the excellent electron mobility of bulk materials (from 5000 to 40.000 cm2 /V.s) and the high electron saturation velocity. We have fabricated ultra-thin body (UTB) InAs/InGaAs MOSFET with gate length of 150 nm. The frequency response and ON-current of the presented MOSFETs is measured and found to have comparable performances to the existing state of the art MOSFETs as reported by the other research groups. The UTB MOSFETs were fabricated by self-aligned method. Two thin body conduction channels were explored, In0,75Ga0,25As and a composite InAs/In0,53Ga0,47As. A thin upper barrier layer consisting of InP (3nm) is inserted between the channel and the oxide layers to realized a buried channel. Finally, the Al2O3 (4 nm) was deposited by the atomic layer deposition (ALD) technique. It is well known that the source and drain (S/D) contact resistances of InAs MOSFETs influence the devices performances. Therefore, in our ultra-thin body (UTB) InAs MOSFETs design, we have engineered the contacts to achieve good ohmic contact resistances. Indeed, for this UTB architecture the use of ion implantation technique is incompatible with a low thermal budget and cannot allow to obtain low resistive contacts. To overcome this limitation, an adapted technological approach to define ohmic contacts is presented. To that end, we chose low thermal budget (250°C) silicide-like technology based on Nickel metal. Finally, we have studied and analyzed the resistance of the alloy between Nickel and III-V (Rsheet). MOSFET with two different epilayer structures (In0,75Ga0,25As and a composite InAs/In0,53Ga0,47As) were fabricated with a gate length (LG) of 150 nm. There were few difference of electrical performance of these two devices. We obtained a maximum drain current (ION) of 730 mA/mm, and the extrinsic transconductance (GM, MAX) showed a peak value of 500 mS/mm. The devices exhibited a current gain cutoff frequency fT of 100 GHz and maximum oscillation frequency fmax of 60 GHz for drain to source voltage (VDS) of 0.7 V.