• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 230
  • 104
  • 71
  • 48
  • 41
  • 18
  • 17
  • 13
  • 8
  • 7
  • 5
  • 5
  • 4
  • 1
  • Tagged with
  • 613
  • 226
  • 167
  • 128
  • 104
  • 96
  • 96
  • 73
  • 70
  • 67
  • 61
  • 54
  • 53
  • 46
  • 41
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
171

Hazard detection with VHDL in combinational logic circuits with fixed delays /

Chu, Ming-Cheung, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 181-182). Also available via the Internet.
172

Representation and simulation of a high level language using VHDL /

Edwards, Carleen Marie, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.
173

VHDL modeling and design of an asynchronous version of the MIPS R3000 microprocessor /

Fanelli, Paul. January 1994 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 124-125).
174

Behavioral delay fault modeling and test generation /

Joshi, Anand Mukund, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 165-169). Also available via the Internet.
175

Efficient VHDL models for various PLD architectures /

Giannopoulos, Vassilis. January 1995 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.
176

Natural language interface to a VHDL modeling tool /

Manek, Meenakshi. January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 79-80). Also available via the Internet.
177

High-Level-Entwurf von Mikrosystemen

Markert, Erik January 2010 (has links)
Zugl.: Chemnitz, Techn. Univ., Diss., 2010
178

Formale Verifikation digitaler Systeme mit Petrinetzen

Schober, Torsten. Unknown Date (has links) (PDF)
Universiẗat, Diss., 2003--Jena.
179

Translating formal specifications into behavioural hardware descriptions

Drögehorn, Olaf. January 2004 (has links)
University, Diss., 2004--Kassel. / Download lizenzpflichtig.
180

VHDL modeling of ASIC power dissipation /

Hoffman, Joseph A. January 1994 (has links)
Report (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 60-62). Also available via the Internet.

Page generated in 0.0551 seconds