Detta är en rapport för ett 15hp examensarbete på Linköpings Tekniska Högskola. Projektet syftar till att implementera ett digitalt frekvensutjämningsfilter för audioapplikationer i ett Atmel DE2 FPGA utvecklingskort. Specifikt ska systemet användas till att korrigera ojämnheter i in-ear hörlurars frekvenssvar. Denna rapport är en beskrivning av systemets utformning och hur arbetet gick till väga. Resultatet blev ett väl fungerande system och ett antal förslag på förbättringar. / This is a report for a 15hp thesis at the Institute of Technology at Linköping University. The project aims to implement a digital frequency-equalizing filter for audio applications in an Atmel DE2 FPGA development board. More specifically the system will be used to correct unevennesses in the frequency response of in-ear earphones. This report is a description of the design of the system and how the work on the project was executed. The result was a well functioning system with suggestions on possible improvements.

Uppgiften var att ta emot och avkoda en radiosignal för tidsangivelse, DCF77. Avkodaren implementerades i en FPGA-krets från ALTERA. Utvecklingen genomfördes i Quartus II-miljön med språket VHDL samt en alternativ lösning där mjuk processor användes. Både utvecklingsmiljön och språken var väl lämpade för uppgiften. Ett genomgående problem var dock radiomottagaren ofta levererade för svag signal för att kunna avkodas korrekt. Under goda mottagningsförhållanden fungerande dock den beskrivna kretsen tillfredsställande.

This thesis is focused on developing a robust algorithm for recognition of road signs including all stages of a machine vision system i.e. image acquisition, pre-processing, colour segmentation, labelling and classifi-cation. Images are acquired by two different imaging systems and noise removal is done by applying Mean filter. Furthermore, different colour segmentation methods are investigated to find out the most high-performance approach and after applying dynamic segmentation based on blue channel in YCbCr colour space, the obtained binary image is transferred to a personal computer through the developed PC software using standard serial port and further processing and classification is run on the PC. Histogram of Oriented Gradients (HOG) is used as the main feature for recognition of road signs and finally the classification task is fulfilled by employing hardware efficient Minimum Distance Classifier (MDC).

Att ett grafikkort ska behandla data och sen generera en bild på en skärm är en ganska logisk funktion för ett grafikkort. Vad som har gjorts här är att alla grundläggande funktioner för grafikkortet har tagits bort, detta för att ingen behandling ska göras. Detta har gjorts för att kunna låta data passera genom kortet med så hög hastighet som möjligt. Att låta data gå genom kortet var det första steget. Efter det skulle förhoppningsvis ett stabilt system ha uppnåtts där vi kunde göra överföringen av data snabbare. Tyvärr blev det inte tillräckligt stabilt och vår slutsats är att man inte kan använda detta kort på det här sättet. För att kunna genomföra detta programmerades FPGA:n med VHDL-kodning. Innan VHDL programmeringen så studerades manualen för kortet för att veta hur de olika registrena på kortet skulle ställas in. För att testa programmering konstruerades en räknare som genererade en trekantsvåg på ett inkopplat oscilloskop. Den ursprungliga uppgiften klarades av. Detta var att skicka igenom data utan den skulle behandlas.

DARC är ett sätt att sända digital information via FM-rundradionätet. Moduleringsmetoden för DARC är GMSK. Målsättningen var att jämföra kostnad/komplexitet och strömförbrukning för olika sätt att demodulera GMSK. Tre icke-koherenta demodulatorer och en koherent demodulator har jämförts. Man vill veta hur stor resursanvändningen var för olika FPGAer. De olika demodulatorerna har beskrivits med VHDL.

Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced. GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload. Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

In this master thesis, a behavioral VHDL model of a 1k Fast Fourier Transform (FFT) algorithm has been improved, first to make it synthesizable and second to obtain a low power consumption. The purpose of the thesis has not been to focus on the FFT algorithm itself or the theory behind it. Instead the aim has been to document and motivate the necessary modifications, to reach the stated requirements, and to discuss the results. The thesis is divided into sections so that the design flow closely can be followed from the initial FFT, down to the final architecture. The two major design steps covered are synthesis and power simulation. The synthesis process has been the most time consuming part of the thesis. The synthesis tool Cadence Ambit PKS was used. Throughout the synthesis, the modifications and solutions will be discussed and comparisons are continuously made between the different solutions and the initial FFT. The best solution will then be the starting point in the next design step, which is simulation of the design with respect to power consumption. This is done by using a simulation tool from Synopsys called NanoSim. Also here, every solution is tested and compared to each other, followed by a concluding discussion. The technology used to implement the design is a 0.35um CMOS process.

This Bachelor thesis is a pre-study of the possibilities of using programmable logic in the purpose to enable fast trigger based data communication. Triggerbased data communication is in this case referred to a context where the processed data is stored and examined so when the trig situation appears the data should be able read out to a computer for evaluating. The purpose of this thesis is to find difficult and time consuming elements but also to find elements that is well suited for implementation in programmable logic. The work should also support further development and verification of trig functionalities and additional hardware. This with the intent of constructing an Ethernet based oscilloscope. The result of this thesis is a conclusion that programmable logic is well suited for many of the implemented logic function

The projects goal is to construct and program a robot that is controlled from a computer but also have an obstacle handling function that allows the robot to navigate around the object by itself. The robot is a simple construction and the number of components and functions is kept at a minimum. A tricycle construction was chosen because it’s the simplest. Communication between the robot and the computer also kept as simple as possible. / Målet med projektet är att konstruera och programmera en robot som går att styra från en dator men det skall även finnas en hinderhanterande funktion som gör att roboten kan åka runt hinder av sig själv. Roboten är en enkel konstruktion där antalet komponenter och funktioner hålls nere till ett minimum. En trehjuling valdes då det är den enklaste konstruktionen. Kommunikationen mellan roboten och datorn hålls också så enkel som möjligt.

The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. The SCI block is able to handle a data rate of 5Mbps in Synchronous mode and 625Kbps in asynchronous mode for a 40MHz clock. It supports five word formats including a multidrop mode for multiprocessor systems. SSI provides a data rate of 10Mbps for the same 40 MHz clock. The design includes a programmable on-chip or external baud rate generator/interrupt timer for the SCI and a clock generator and frame Sync generator for the SSI. The thesis focus on arriving at a full functional description of individual blocks included with Port C from the data sheets and product users manual. From this operational description a behavioural model was developed. The structure and implementation is based on the Motorola DSP56002 with additional support for a variable data-width. The model is written completely in behavioural VHDL with a top-down approach and the model was verified and validated.