The goal of this research was to explore a new and improved software development tool for the implementation of control algorithms on Xilinx Field Programmable Gate Arrays (FPGA). The Simulink plug in, System Generator, complements traditional Hardware Description Language (HDL) by providing a higher level graphical language for the development of FPGA designs. The design is then translated into the lower level required by the Xilinx's ISE program. By utilizing this graphical based higher level of abstraction at the design entry level, the requirement of a detailed knowledge of HDL languages is no longer required. Because of this new environment the time required to implement the previously developed control design on the FPGA is reduced. The initial work began with a study of System Generator capabilities. One of the primary areas of interest is the difference on how the mathematical model representations are implemented between Simulink and the logic based hardware. From this initial work, a methodology for conversion between the developed and verified Simulink design and hardware implementation was obtained. As a case study, a control design was implemented for a Simulink model of an Unmanned Ground Vehicle (UGV) based on an RC-Truck. The control system consists of a simple mission planner to generate a vector of waypoints, a proportional-integral velocity controller and a proportional heading controller. The derived hardware design process is then utilized and validated by converting the control system into the available System Generator blocks. The final verification of the FPGA design was a hardware-in-the-loop simulation utilizing a Xilinx prototyping board. This design example demonstrated the validity of the presented approach as an efficient and reliable method for rapid system prototyping for designs developed within the Simulink environment.

Κύριος σκοπός της εργασίας είναι η υλοποίηση ενός υπολογιστικού συστήματος με Scratch pad μνήμη και η διαχείριση της μνήμης μέσω ενσωματωμένου λογισμικού. Αρχικά παρουσιάζονται τα πλεονεκτήματα και τα μειονεκτήματα ενός συστήματος που χρησιμοποιεί μνήμη Scratch pad σε σύγκριση με ένα αντίστοιχο σύστημα με cache. Μετά σχεδιάζουμε το σύστημα μας χρησιμοποιώντας την γλώσσα περιγραφής υλικού VHDL και λαμβάνουμε πειραματικές μετρήσεις οι οποίες προκύπτουν από την μέτρηση των κύκλων εκτέλεσης ενός αντιπροσωπευτικού προγράμματος. Η προτεινόμενη αρχιτεκτονική με Scratch pad και η τεχνική προγραμματισμού της αποφέρουν μια βελτίωση της απόδοσης κατά 36% σε σχέση με την αντίστοιχη αρχιτεκτονική με cache. Αυτό οφείλεται στις σημαντικά λιγότερες αστοχίες που παρουσιάζει η Scratch pad όταν προγραμματιστεί κατάλληλα καθώς ο DMA ελεγκτής έχει τη δυνατότητα να μεταφέρει τα δεδομένα παράλληλα με την εκτέλεση του προγράμματος. / The main purpose of this master thesis is the implementation of a computer system using scratch pad memory including memory management via embedded software. Initially we present the pros and cons of a system using scratch pad memory, in comparison to a system using cache memory. We then design our system using the hardware description language VHDL and we compare the performance with an equivalent architecture using cache memory. This is done by counting the clock cycles needed in order to run a sample program. The proposed scratch pad architecture and the programming technique used produced a 36% better performance in comparison to an equivalent cache memory architecture. This is due to the less misses that a scratch pad memory presents, when programmed efficiently.

Total ionizing dose (TID) radiation effects modeling and simulation on digital, analog and mixed signal systems remains a significant bottle neck in the development of radiation-hardened electronics. Unverified modeling techniques and the very high computational cost with today's commercial simulation tools are among the primary hindrances to the timely hardened IC design, particularly to the design in commercially available processes. SPICE-based methods have been used for total dose radiation degradation simulations. While SPICE is effective in predicting the circuit behavior under circumstances when the electrical parameters stay constant during operation, it's not effective predicting aging behavior with gradual change with time. Behavioral modeling language, such as VHDL-AMS is needed to effectively capture the time-dependent degradation in these parameters in response to environmental stresses, such as TID radiation.This dissertation describes a method for accurate and rapid TID effect simulation of complex mixed-signal circuits. The method uses a hierarchical structure where small sub-circuits, such as voltage comparators, references, etc. are simulated using SPICE. These SPICE simulations of small circuits for multiple radiation doses are used to tune behavioral VHDL-AMS models for the sub-circuits. The created behavioral models therefore contain the electrical circuit behavior combined with the radiation response. The entire combined system is then simulated using VHDL-AMS.In a simulation experiment that was used to validate the speed and accuracy of the new method, a commercial 8-bit sub-ranging analog to digital converter netlist containing more than 2000 MOS transistors was simulated with TID models using a contemporary SPICE-based method and the new method. The new method shortened the simulation time by three orders of magnitude, while accuracy remained within reasonable limits compared to the SPICE-based method. Moreover, the automated procedures for circuit node bias monitoring, TID model replacement and result collection that are included in the simulation code of the new method decreased the "hands-on" engineering work significantly. Results from an experiment where the new TID effect simulation method was used as a hardness assurance test procedure for integrated circuits designed to be operated in radiation-harsh environments are also included in this dissertation.

Image processing emerges from the curiosity of human vision. To translate, what we see in everyday life and how we differentiate between objects, to robotic vision is a challenging and modern research topic. This thesis focuses on detecting a pedestrian within a standard format of an image. The efficiency of the algorithm is observed after its implementation in FPGA. The algorithm for pedestrian detection was developed using MATLAB as a base. To detect a pedestrian, a histogram of oriented gradient (HOG) of an image was computed. Study indicates that HOG is unique for different objects within an image. The HOG of a series of images was computed to train a binary classifier. A new image was then fed to the classifier in order to test its efficiency. Within the time frame of the thesis, the algorithm was partially translated to a hardware description using VHDL as a base descriptor. The proficiency of the hardware implementation was noted and the result exported to MATLAB for further processing. A hybrid model was created, in which the pre-processing steps were computed in FPGA and a classification performed in MATLAB. The outcome of the thesis shows that HOG is a very efficient and effective way to classify and differentiate different objects within an image. Given its efficiency, this algorithm may even be extended to video.

As network hardware has become faster, inefficient communication and synchronization mechanisms often have proven to be fast enough but better models are needed in order to support future systems. The aggregate function communication model, and the KAPERS design and implementation presented in this thesis, provide more efficient ways to implement a wide range of higher-level communication and synchronization operations. The main contributions of this work center on a new way to use FPGA-based memory in an aggregate function network (AFN). The basic functions were designed and implemented with modal encoding to create a global memory that allows variable length objects and object addresses. New and enhanced algorithms were written for use with the new AFN architecture. This thesis also details the KAPERS prototype hardware implementation.

Processors used in lower-end scientific applications like graphic cards and video game consoles have IEEE single precision floating-point hardware [23]. Double precision offers higher precision at higher implementation cost and lower performance. The need for high precision computations in these applications is not enough to justify the use double precision hardware and the extra hardware complexity needed [23]. Native-pair arithmetic offers an interesting and feasible solution to this problem. This technique invented by T. J. Dekker uses single-length floating-point numbers to represent higher precision floating-point numbers [3]. Native-pair arithmetic has been proposed by Dr. William R. Dieter and Dr. Henry G. Dietz to achieve better accuracy using standard IEEE single precision floating point hardware [1]. Native-pair arithmetic results in better accuracy however it decreases the performance by 11x and 17x for addition and multiplication respectively [2]. The proposed implementation uses a residual register to store the error residual term [2]. This addition is not only cost efficient but also results in acceptable accuracy with 10 times the performance of 64-bit hardware. This thesis demonstrates the implementation of a 32-bit floating-point unit with residual register and estimates the hardware cost and performance.

Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of a particular function is realized in software or hardware. The designer can then model/evaluate a given system design approach and later allocate functions to software and hardware, as appropriate to meet constraints such as performance, cost, schedule. Since using UML for software is a standard approach, this research investigates the UML to hardware path via VHDL. / Department of Computer Science

The following dissertation attempts to highlight and address the implementation and performance of a Kalman filter on an FPGA. The reasons for choosing the Kalman filter and the platform for implementation are highlighted as well as an in depth explanation of the components and theory behind both are given. A controller system which allows the optimal performance of the Kalman filter on it is developed in VHDL. The design of the controller is dictated by the analysis of the Kalman filter which ensures only the most necessary components and operations are built into the instruction set. The controller is made up of several components including the loader, the ALU, Data RAM, KF IO, Control Store and the Branch Unit. The components working in conjunction allows the system to interface though a handshaking protocol with a peripheral of arbitrary latency. The control store is loaded with program code that is determined by converting human readable assembler into machine code through a Perl encoder. The controller system is tested and verified though an extensive testbench environment that emulates all outside signals and views internal operations. The controller system is capable of five matrix operations which are computed in parallel due to the FPGA development environment, which is far superior in this case to the alternative: a software solution, due to the vector operations inherent in the Kalman filter algorithm. The Kalman filter operation is analyzed and simulated in a MATLAB environment and this analysis confirms the need for the parallel processing power of the FPGA system upon which the controller has been built. FPGA statistical analysis confirms the successful implementation of the system meeting all criteria set at the outset of the project, including memory usage, IO usage and performance and accuracy benchmarks. / Graduate

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 52-54). Also available via the Internet.

Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (p. 69-72).