NDLTD Global ETD Search
  • Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 205
  • 72
  • 64
  • 50
  • 25
  • 21
  • 15
  • 10
  • 6
  • 3
  • 3
  • 3
  • 3
  • 2
  • 2
  • Tagged with
  • 680
  • 197
  • 162
  • 136
  • 135
  • 134
  • 127
  • 124
  • 118
  • 85
  • 81
  • 75
  • 73
  • 69
  • 59
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

Search results

Showing 241 to 250 of 680 (0.23 seconds)

Spelling suggestions: "subject:"vliv""

241

A Novel Simulation Based Approach for Trace Signal Selection in Silicon Debug

Komari, Prabanjan 20 October 2016 (has links)
No description available.
Electrical Engineering
VLSI
EDA
CAD
Post Silicon debug
Functional Validation
242

Efficient branch and bound algorithm for the dynamic layout problem

Jariwala, Anish January 1995 (has links)
No description available.
Engineering, Industrial
VLSI
Facility Layout
Cplex Preprocessing Rules
243

One-dimensional compaction strategy for VLSI symbolic layout system

Kim, Cheongbu January 1988 (has links)
No description available.
One-Dimensional Compaction Strategy
VLSI
Symbolic Layout System
244

A VLSI design of a finite impulse response low-pass digital filter

Talej, Elie N. January 1988 (has links)
No description available.
VLSI
Finite Impulse Response
Low-Pass Digital Filter
245

Scan path design of PLA to improve its testability in VLSI realization

Chiang, Kang-Chung January 1986 (has links)
No description available.
Scan Path Design
PLA to Improve Testability
VLSI Realization
246

A VLSI-nMOS hardware implementation of an IIR bandpass orthogonal digital filter

Kaake, Fadi M. January 1986 (has links)
No description available.
A VLSI-nMOS Hardware Implementation
IIR Bandpass Orthogonal Digital Filter
247

A VLSI-nMOS hardware implementation of a high speed parallel adder

Taesopapong, Somboom January 1986 (has links)
No description available.
A VLSI-nMOS Hardware Implementation
High Speed Parallel Adder
248

Parallel processing and VLSI design: Solving large-scale linear systems

Schwarz, Eric M. January 1984 (has links)
No description available.
Parallel Processing Methods
VLSI
Large-Scale Linear Systems
249

VLSI NMOS hardware design of a linear phase FIR low pass digital filter

Chabbi, Charef January 1985 (has links)
No description available.
Integer Linear Programming
FIR
250

Implementation of basic software tools to start a VLSI program at Ohio University with a high speed parallel multiplier as an example

Choudhury, Niren Ch. January 1985 (has links)
No description available.
VLSI
High Speed Parallel Multiplier
UNIX Operating System

Page generated in 0.2336 seconds