Current day VLSI systems have started seeing increasing percentages of multiple energy domain components being integrated into the mainstream. Energy domains such as mechanical, optical, fluidic etc. have become all pervasive into VLSI systems and such systems are being manufactured routinely. The framework required to design such an integrated system with diverse energy domains needs to be evolved as a part of conventional VLSI design methodology. This is because manufacturing and design of these integrated energy domains although based on semiconductor processing, is still very ad-hoc, with each device requiring its dedicated design tools and process integration. In this thesis three different approaches in different energy domains, have been pro-posed. These three domains include modelling & simulation, synthesis & compilation and formal verification. Three different scenarios have been considered and it is shown that these tasks can be co-performed along with conventional VLSI circuits and systems. In the first approach a micro-mechanical beam bending case is presented. A thermal heat ow causing the beam to bend through thermal stress is analyzed for change in capacitance under a single analysis and modelling framework. This involves a seamless analysis through thermal, mechanical and electrical energy domains. The second part of the thesis explores synthesis and compilation paradigms. The concept of a Gyro-compiler analogous to a memory compiler is proposed, which primarily generates soft IP models for various gyro topologies. The final part of this thesis deals in showcasing a working prototype of a formal verification framework for MEMS based hybrid systems. The MEMS verification domain today is largely limited to simulation based verification. Many techniques have been proposed for formal verification of hybrid systems. Some of these methods have been extended to demonstrate, how MEMS based hybrid systems can be formally verified through ex-tensions of conventional formal verification methods. An adaptive cruise control (ACC) system with a gyro based speed sensor has been analyzed and formally verified for various specifications of this system.

Les circuits logiques programmables (FPGA) bénéficient des technologies les plus avancés de noeuds CMOS, afin de répondre aux demandes croissantes de haute performance et de faible puissance des circuits intégrés numériques. Cela les rend sensibles aux différents mécanismes de dégradations à l'échelle nanométrique. Dans cette thèse, nous nous concentrons sur le vieillissements des tables de correspondances (LUT) sur FPGA. L'utilisation de la dernière technologie d'échelle réduite et la flexibilité de l'architecture du FPGA, permettent de développer un nouveau banc de test à faible coût pour évaluer la fiabilité en fonction de conditions d'utilisations. Ce banc de test peut-être implanté sur plusieurs véhicules du tests et suivis en temps réel par un logiciel de surveillance développé pendant cette thèse. Nous avons caractérisé la dégradation de temps de propagation de la LUT en fonction du rapport cyclique et la fréquence des vecteurs de stress. Nous avons identifié également que le rapport cyclique affecte fortement le temps en descente et modérément le temps en montée de LUT en raison du mécanisme de vieillissement NBTI, tandis que HCI affecte à la fois les deux temps de propagation. En outre, deux modèles semi-empiriques de la dégradation du temps de propagation de la LUT en raison de NBTI et HCI sont proposés dans ce travail. D'autre part, nous avons analysé l'influence de la tension de seuil et la mobilité du transistor sur la dégradation de temps de propagation de la LUT en utilisant le modèle de simulation du transistor. Enfin, un modèle de dégradation de la LUT prenant en compte l'architecture supposée de la LUT est proposé. Ce travail est idéal pour modéliser la dégradation des FPGA au niveau des portes. / Field-Programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated cricuits. This makes tem sensible to various aging mechanisms at nanao-scale. In this thesis we focus on aging degradation of the Look-Up Table (LUT) on FPGAs. Benefits from the latest downscaling technology and the flexibility of the FPGAs architecture, allow to develop a new low cost test bench to assess reliabilty depending on the operation condition. This test bench can be implemented on up to 32 FPGAs ans monitored in real time by a supervisory software we developed in this work. We have characterized the delay degradation of LUT depending on the duty cycle and the frequency of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanisme, while HCI affects both delays. Furthermore, two semiempirical models of the degradation of LUT timing due to NBTI and HCI are proposed in this work. Moreover, we analyzed the influence of threshokd voltage and the mobility of transistor on the timing degradation of LUT using the simulation model of transistor. Finally a model of degradationof LUT taking into account the supposed LUT architecture has been proposed. This work is edeal to model the degradation of FPGA at gate level.

Der Asynchronous Transfer Mode (ATM) stellt die zukünftige und einheitliche Basistechnologie für das Breitband-ISDN dar. Da nahezu alle wesentlichen Protokollfunktionen in Hardware realisierbar sind, soll nachfolgend ein Überblick über bereits angebotene VLSI-Schaltkreise gegeben werden. Eine Systematisierung und Einordnung vorhandener ATM-Chips hinsichtlich ihrer Leistungsfähigkeit und ihres Funktionsumfangs erfolgt in Hinblick auf das sogenannte B-ISDN-Referenzmodell. Dieses Schichtenmodell definiert die notwendigen Protokolle und Schnittstellen für den Asynchronous Transfer Mode. Zum grundlegenden Verständnis wird einleitend eine kurze Einführung in die Basisprinzipien von ATM gegeben.

LSTM neural networks have been used for speech recognition, image recognition and other artificial intelligence applications for many years. Most applications perform the LSTM algorithm and the required calculations on cloud computers. Off-line solutions include the use of FPGAs and GPUs but the most promising solutions include ASIC accelerators designed for this purpose only. This report presents an ASIC design capable of performing the multiple iterations of the LSTM algorithm on a unidirectional and without peepholes neural network architecture. The proposed design provides arithmetic level parallelism options as blocks are instantiated based on parameters. The internal structure of the design implements pipelined, parallel or serial solutions depending on which is optimal in every case. The implications concerning these decisions are discussed in detail in the report. The design process is described in detail and the evaluation of the design is also presented to measure accuracy and error of the design output.This thesis work resulted in a complete synthesizable ASIC design implementing an LSTM layer, a Fully Connected layer and a Softmax layer which can perform classification of data based on trained weight matrices and bias vectors. The design primarily uses 16-bit fixed point format with 5 integer and 11 fractional bits but increased precision representations are used in some blocks to reduce error output. Additionally, a verification environment has also been designed and is capable of performing simulations, evaluating the design output by comparing it with results produced from performing the same operations with 64-bit floating point precision on a SystemVerilog testbench and measuring the encountered error. The results concerning the accuracy and the design output error margin are presented in this thesis report. The design went through Logic and Physical synthesis and successfully resulted in a functional netlist for every tested configuration. Timing, area and power measurements on the generated netlists of various configurations of the design show consistency and are reported in this report. / LSTM neurala nätverk har använts för taligenkänning, bildigenkänning och andra artificiella intelligensapplikationer i många år. De flesta applikationer utför LSTM-algoritmen och de nödvändiga beräkningarna i digitala moln. Offline lösningar inkluderar användningen av FPGA och GPU men de mest lovande lösningarna inkluderar ASIC-acceleratorer utformade för endast dettaändamål. Denna rapport presenterar en ASIC-design som kan utföra multipla iterationer av LSTM-algoritmen på en enkelriktad neural nätverksarkitetur utan peepholes. Den föreslagna designed ger aritmetrisk nivå-parallellismalternativ som block som är instansierat baserat på parametrar. Designens inre konstruktion implementerar pipelinerade, parallella, eller seriella lösningar beroende på vilket anternativ som är optimalt till alla fall. Konsekvenserna för dessa beslut diskuteras i detalj i rapporten. Designprocessen beskrivs i detalj och utvärderingen av designen presenteras också för att mäta noggrannheten och felmarginal i designutgången. Resultatet av arbetet från denna rapport är en fullständig syntetiserbar ASIC design som har implementerat ett LSTM-lager, ett fullständigt anslutet lager och ett Softmax-lager som kan utföra klassificering av data baserat på tränade viktmatriser och biasvektorer. Designen använder huvudsakligen 16bitars fast flytpunktsformat med 5 heltal och 11 fraktions bitar men ökade precisionsrepresentationer används i vissa block för att minska felmarginal. Till detta har även en verifieringsmiljö utformats som kan utföra simuleringar, utvärdera designresultatet genom att jämföra det med resultatet som produceras från att utföra samma operationer med 64-bitars flytpunktsprecision på en SystemVerilog testbänk och mäta uppstådda felmarginal. Resultaten avseende noggrannheten och designutgångens felmarginal presenteras i denna rapport.Designen gick genom Logisk och Fysisk syntes och framgångsrikt resulterade i en funktionell nätlista för varje testad konfiguration. Timing, area och effektmätningar på den genererade nätlistorna av olika konfigurationer av designen visar konsistens och rapporteras i denna rapport.

Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. However, the hardware cost of ASIC based methods and related interface is considerably high to be integrated into coarse grain reconfigurable architectures (CGRA). Moreover, for platforms aiming at high level synthesis or system level synthesis, they don’t provide flexibility under low-performance low-cost design scenarios. In this degree project, we establish connectivity between SiLago CGRA and a typical QC-LDPC code defined in IEEE 802.11n standard. We design lightweight LDPC encoder and decoder blocks using FSM+Datapath design pattern. The encoder provides sufficient throughput and consumes very little area and power. The decoder provides sufficient performance for low speed modulations while consuming significantly lower hardware resources. Both encoder and decoder are capable of cooperating with SiLago based DRRA through standard Network on Chip (NOC) based shared memory, DiMArch. And extra hardware for interface is no longer necessary. We verified our design through RTL simulation and synthesis. Encoder went through logic and physical synthesis while decoder went through only logic synthesis. The result acquired proves that our design is closely coupled with the SiLago CGRA while provides a solution with lowperformance and low-cost. / LDPC-kod med låg densitet är en felkorrigeringskod som har vidtagits i stor utsträckning som en valfri felsökande operation i de flesta av dagens kommunikationsprotokoll. Nuvarande design av ASICeller FPGAbaserade LDPC-acceleratorer kan nå Gbit / s datahastighet. Hårdvarukostnaden för ASIC-baserade metoder och relaterade gränssnitt är emellertid avsevärt hög för att integreras i grova kornkonfigurerbara arkitekturer (CGRA). Dessutom ger plattformar som syftar till syntese på hög nivå eller syntes på systemnivå inte flexibilitet under lågprestanda med låg kostnadsscenarier. I detta examensarbete upprättar vi anslutning mellan SiLago CGRA och en typisk QC-LDPC-kod definierad i IEEE 802.11n-standarden. Vi designar lätta LDPC-kodare och avkodarblock med FSM + Datapathdesignmönster. Kodaren ger tillräcklig genomströmning och förbrukar mycket lite areal och effekt. Avkodaren ger tillräckligt med prestanda för moduleringar med låg hastighet medan den förbrukar betydligt lägre hårdvaruressurser. Både kodare och avkodare kan samarbeta med SiLago-baserade DRRA genom standard Network on Chip (NOC) baserat delat minne, DiMArch. Och extra hårdvara för gränssnittet är inte längre nödvändigt. Vi verifierade vår design genom RTL-simulering och syntes. Kodaren genomgick logik och fysisk syntes medan avkodare genomgick endast logisk syntes. Det förvärvade resultatet bevisar att vår design är nära kopplad till SiLago CGRA och ger en lösning med låg prestanda och låg kostnad.

The main objectives of this dissertation is to investigate the prospects of embedded thermoelectric devices integrated in a chip package and to develop a design methodology aimed at taking advantage of the on-chip on-demand cooling capabilities of the thermoelectric devices. First a simulation framework is established and validated against experimental results, which helps to study the cooling capabilities of embedded thermoelectric coolers (TEC) in both a transient and steady state. The potential for up to 15°C of total cooling has been shown. The thermal simulation framework allows for rapid assessment of TEC and system level thermal performance. Next, the thesis develops a co-simulation environment that is capable of simulating the thermal and electrical domain and couples them to design intelligent TEC controllers. These controllers are implemented on chip and can leverage the transient cooling capability of the device. The controllers are simulated within the co-simulation environment and their potential to control high power chip events are thoroughly investigated. The system level overheads are considered and discussions on implementation techniques are presented. The co-simulation framework is also extended to allow for simulation of real predictive technology microprocessor cores and their workloads. Finally the thesis implements a fully on-chip autonomous energy system that takes advantage of the TEC in its reverse energy harvesting mode and uses the same device to harvest energy and use the energy to power the on-chip cooling circuit. This increases the overall energy efficiency of the cooler and verifies the TEC control methods.

本論文共一冊，約六萬字，分六章二十三節。 第一章緒論：說明本論文研究背景，研究動機與目的並列示本論文整體性架構。 第二章理論基礎：指出創業投資之意義、程序、功能與特性，並就策略觀點探討創業 投資方案之評估。 第三章文獻探討：就國內外有關創業投資活動的文獻，加以整理比較。 第四章研究方法：揭示本論文研究架構，變數說明、研究設計與研究限制。 第五章實證分析與發現：提出模型研究結果，以說明創業投資方案之評估重點，以及 試圖導出一個參考模式，以為企業界之應用。 第六章結論與建議：根據研究結果，指出評估創業投資方案之注意事項與本研究之應 用，以及對後續研究之建議。

L'évolution des technologies microélectroniques augmente la sensibilité des circuits intégrés face aux perturbations (impact de particules, perte de l'intégrité du signal...). Le comportement erroné d'un circuit peut être inacceptable et une analyse de sûreté à haut niveau d'abstraction permet de choisir les protections les plus adaptées et de limiter le surcoût induit par une éventuelle reprise de la description. Cette thèse porte sur le développement d'une méthodologie et d'un environnement améliorant l'étude de la robustesse de circuits intégrés numériques. L'approche proposée met en œuvre un prototype matériel d'une version instrumentée du circuit à analyser. L'environnement comprend trois niveaux d'exécution dont un niveau logiciel embarqué qui permet d'accélérer les expériences en conservant une grande flexibilité : l'utilisateur peut obtenir le meilleur compromis entre complexité de l'analyse et durée des expériences. Nous proposons également de nouvelles techniques d'instrumentation et de contrôle des injections afin d'améliorer les performances de l'environnement. Une évaluation prédictive de ces performances renseigne l'utilisateur sur les paramètres les plus influents et sur la durée de l'analyse pour un circuit et une implantation de l'environnement donnés. Enfin la méthodologie est appliquée pour l'analyse de deux systèmes significatifs dont un système matériel/logiciel construit autour d'un microprocesseur SparcV8.

A generalised model of biological topographic map development is presented which combines both weight plasticity and the formation and elimination of synapses (synaptic rewiring) as well as both activity-dependent and -independent processes. The question of whether an activity-dependent process can refine a mapping created by an activity-independent process is investigated using a statistical approach to analysingmapping quality. The model is then implemented in custom mixed-signal VLSI. Novel aspects of this implementation include: (1) a distributed and locally reprogrammable address-event receiver, with which large axonal fan-out does not reduce channel capacity; (2) an analogue current-mode circuit for Euclidean distance calculation which is suitable for operation across multiple chips; (3) slow probabilistic synaptic rewiring driven by (pseudo-)random noise; (4) the application of a very-low-current design technique to improving the stability of weights stored on capacitors; (5) exploiting transistor non-ideality to implement partially weightdependent spike-timing-dependent plasticity; (6) the use of the non-linear capacitance of MOSCAP devices to compensate for other non-linearities. The performance of the chip is characterised and it is shown that the fabricated chips are capable of implementing the model, resulting in biologically relevant behaviours such as activity-dependent reduction of the spatial variance of receptive fields. Complementing a fast synaptic weight change mechanism with a slow synapse rewiring mechanism is suggested as a method of increasing the stability of learned patterns.

Geometric packing problems are NP-complete problems that arise in VLSI design. In this thesis, we present two novel algorithms using dynamic programming to compute exactly the maximum number of k x k squares of unit size that can be packed without overlap into a given n x m grid. The first algorithm was implemented and ran successfully on problems of large input up to 1,000,000 nodes for different values. A heuristic based on the second algorithm is implemented. This heuristic is fast in practice, but may not always be giving optimal times in theory. However, over a wide range of random data this version of the algorithm is giving very good solutions very fast and runs on problems of up to 100,000,000 nodes in a grid and different ranges for the variables. It is also shown that this version of algorithm is clearly superior to the first algorithm and has shown to be very efficient in practice.