Le problème de la synthèse automatique de circuits est aborde ici à travers trois experiences de réalisation de compilateurs. La première concerne la traduction de la spécification fonctionnelle d'un circuit décrit en Lascar ( langage de la famille cascade). Le deuxième compilateur utilise un formalisme de règles de réécriture pour produire un circuit adapte à une bibliothèque spécifique de Bull-systèmes, a partir d'une description en langage Lds. La troisième expérience aborde le problème de la synthèse de parties opératives, dont les principales difficultés sont présentées en détail. La méthode utilisée met en œuvre un algorithme de séquencement fonde sur un formalisme potentiel-tache, et une méthode de partage de registres et d'allocation d'opérateurs a partir d'un algorithme de coloriage de graphes

Cette thèse présente l'introduction de méthodes nouvelles dans le domaine de la conception assistée par ordinateur de circuits à haute intégration. A partir de la description d'un ensemble d'individus par la liste de leurs corrélations (ou distances) deux à deux, l'analyse factorielle de données se propose d'en fournir une représentation planaire. Le but de cette thèse est de décrire le cheminement parcouru pour pouvoir utiliser ces méthodes connues depuis longtemps des statisticiens, dans le domaine de la génération de plans de masse. Ainsi, plusieurs idées originales permettant l'utilisation d'algorithmes classiques d'analyse factorielle de données dans le cadre de la CAO de circuits sont présentées. Ces idées sont concrétisées par la réalisation et la présentation d'un logiciel de génération de plans de masse

Étude des évaluations électriques et temporelles des PLA (NMOS, CMOS, bipolaires) complexes. Étude d'un outil prototype d'évaluation capable de calculer les paramètres électriques et topologiques et d'estimer le temps de propagation dans les PLA. On isole les paramètres qui donnent des degrés de libertés ; on obtient le choix des compromis de réalisation d'un PLA particulier à partir d'abaques, générés par le système. L'utilisateur peut alors choisir l'organisation d'un PLA particulier en fonction de sa consommation, de sa fiabilité logique et de son temps de réponse.

Le contexte des applications de communication visuelle évolue vers l'introduction de fonctionnalités qui dépassent la simple compression d'images: accès universel, interactivité basée-contenu, intégration de contenus hybrides synthétiques-naturels. Une brève introduction au codage avancé d'images permet d'entrevoir l'évolution de la puissance de calcul et de la généricité requises pour l'implémentation de ces systèmes de "deuxième génération". Une synthèse sur l'évolution des circuits VLSI dédiés à l'analyse, la compression et le rendu d'images permet une réflexion sur les limitations architecturales des "processeurs multimédia". Cette thèse propose de combiner le parallélisme massif et l'asynchronisme à grain fin pour apporter de nouvelles perspectives de conception conjointe d'algorithmes et d'architectures VLSI numériques. Une introduction aux différentes notions d'asynchronisme, aux niveaux langage, algorithme, architecture, circuit VLSI, permet de mieux cerner leur sens et les potentiels qu'elles offrent. L'application d'un asynchronisme fonctionnel au filtrage morphologique d'images a abouti à la réalisation d'un réseau VLSI cellulaire asynchrone spécifique comprenant 800.000 transistors en technologie CMOS 0.5µ. La combinaison du parallélisme et de l'asynchronisme est finalement généralisée à travers la définition d'une architecture de coprocesseur programmable pour l'analyse-rendu d'images. L'évaluation de plusieurs primitives algorithmiques originales, basées sur un contrôle mixte SPMD-cellulaire-associatif-flot de données, illustre l'utilisation conjointe de l'asynchronisme à différents niveaux. Ce travail démontre que le relâchement des contraintes de synchronisation et de séquencement, de la spécification à la réalisation matérielle, favorise l'exploitation du parallélisme inhérent aux algorithmes et des potentiels des technologies VLSI.

<p>An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design. </p><p>Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippetsinto actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated. </p><p>Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible. </p><p>The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of implementation, to check the chip design for DRC and LVS errors.</p>

<p>This thesis investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer. </p><p>The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can. </p><p>Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.</p>

For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a real-time analog VLSI chip which estimates the focus of expansion (FOE) from measured time-varying images. Our approach assumes a camera moving through a fixed world with translational velocity; the FOE is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the FOE gives the direction of 3-D translation. The algorithm we use for estimating the FOE minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the FOE. This minimization is not straightforward, because the relationship between the brightness derivatives depends on the unknown distance to the surface being imaged. However, image points where brightness is instantaneously constant play a critical role. Ideally, the FOE would be at the intersection of the tangents to the iso-brightness contours at these "stationary" points. In practice, brightness derivatives are hard to estimate accurately given that the image is quite noisy. Reliable results can nevertheless be obtained if the image contains many stationary points and the point is found that minimizes the sum of squares of the perpendicular distances from the tangents at the stationary points. The FOE chip calculates the gradient of this least-squares minimization sum, and the estimation is performed by closing a feedback loop around it. The chip has been implemented using an embedded CCD imager for image acquisition and a row-parallel processing scheme. A 64 x 64 version was fabricated in a 2um CCD/ BiCMOS process through MOSIS with a design goal of 200 mW of on-chip power, a top frame rate of 1000 frames/second, and a basic accuracy of 5%. A complete experimental system which estimates the FOE in real time using real motion and image scenes is demonstrated.

This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor.

We present novel architectures for parallel-node low-density parity-check convolutional code (PN-LDPC-CC) encoders and decoders. Based on a recently introduced implementation-aware class of LDPC-CCs, these encoders and decoders take advantage of increased node-parallelization to simultaneously decrease the energy-per-bit and increase the decoded information throughput. A series of progressively improved encoder and decoder designs are presented and characterized using synthesis results with respect to power, area and throughput. The best of the encoder and decoder designs significantly advance the state-of-the-art in terms of both the energy-per-bit and throughput/area metrics. One of the presented decoders, for an Eb /N0 of 2.5 dB has a bit-error-rate of 106, takes 4.5 mm2 in a CMOS 90-nm process, and achieves an energy-per-decoded-information-bit of 65 pJ and a decoded information throughput of 4.8 Gbits/s. We implement an earlier non-parallel node LDPC-CC encoder, decoder and a channel emulator in silicon. We provide readers, via two sets of tables, the ability to look up our decoder hardware metrics, across four different process technologies, for over 1000 variations of our PN-LDPC-CC decoders. By imposing practical decoder implementation constraints on power or area, which in turn drives trade-offs in code size versus the number of decoder processors, we compare the code BER performance. An extensive comparison to known LDPC-BC/CC decoder implementations is provided.

Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist sampling rate. In CS, the signal is not directly acquired but reconstructed from a few measurements. One of the key problems in CS is how to recover the original signal from measurements in the presence of noise. This dissertation addresses signal reconstruction problems in CS. First, a feedback structure and signal recovery algorithm, orthogonal pruning pursuit (OPP), is proposed to exploit the prior knowledge to reconstruct the signal in the noise-free situation. To handle the noise, a noise-aware signal reconstruction algorithm based on Bayesian Compressed Sensing (BCS) is developed. Moreover, a novel Turbo Bayesian Compressed Sensing (TBCS) algorithm is developed for joint signal reconstruction by exploiting both spatial and temporal redundancy. Then, the TBCS algorithm is applied to a UWB positioning system for achieving mm-accuracy with low sampling rate ADCs. Finally, hardware implementation of BCS signal reconstruction on FPGAs and GPUs is investigated. Implementation on GPUs and FPGAs of parallel Cholesky decomposition, which is a key component of BCS, is explored. Simulation results on software and hardware have demonstrated that OPP and TBCS outperform previous approaches, with UWB positioning accuracy improved by 12.8x. The accelerated computation helps enable real-time application of this work.